Shared Memory Mode Example; Master Device Program - Intel 8XC196NT User Manual

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9.4.2

Shared Memory Mode Example

In shared memory mode, the master and slave share a 256-byte block of memory. The high byte
of the address (the base address) controls the location within the slave device memory space. The
low byte of the address is always in the SLP_CMD register. The P3_REG register contains data
to be read; the P3_PIN register contains the data written. This mode requires a multiplexed bus.
The primary difference between this mode and the standard slave mode is in the way that the ad-
dress is loaded into the SLP_CMD register. The low byte of the address is automatically loaded
into SLP_CMD on the falling edge of SLPALE. The data is latched on the rising edge of SLPRD#
or SLPWR#. For this reason, a write or read operation requires only one master bus cycle rather
than two and three bus cycles, respectively, in standard slave mode.
The time between the falling edge of SLPALE and the rising edge of SLPRD# is too short to allow
the slave processor to perform the read. Therefore, reads are pipelined in this mode, as they are
in standard slave mode. When the master requests a read operation, the data present during the
current bus cycle is either "dummy" data or the data from the previous read operation. Although
read operations are pipelined, write operations are not. Therefore, write operations can be per-
formed between reads without corrupting data that is waiting to be read. This allows the master
to assign higher priority to write cycles. The master must wait for SLPINT to go high between
reads or writes.
In this example, the master and slave share a 256-byte block of memory from 0400–04FFH.
9.4.2.1

Master Device Program

In this mode, the master simply requests a read and receives data one bus cycle following the pre-
vious read. The following code segment illustrates how this is done.
OFFSET
EQU
0FF00H
ADD
ADDR,#OFFSET
LDB
DATA,[ADDR]
The data that is read is actually the data from the previous read cycle. The address driven causes
the slave to perform an interrupt service routine to fetch the data at that address. The data at the
address is valid on the rising edge of SLPINT. Writing to the slave is equally simple, as the fol-
lowing code segment illustrates.
OFFSET
EQU
0FF00H
ADD
ADDR,#OFFSET
STB
DATA,[ADDR]
; point to the external address
; read the slave device data
; point to the slave address
; store data at the address
SLAVE PORT
9-11

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