Intel 8XC196NT User Manual page 130

PTS Block Transfer Mode Control Block
In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and
destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count
(PTSCOUNT).
7
Unused 0
7
PTSBLOCK
15
PTSDST (HI)
7
PTSDST (LO)
15
PTSSRC (HI)
7
PTSSRC (LO)
7
PTSCON M2
7
PTSCOUNT
Register Location
PTSBLOCK PTSCB + 6
PTSDST PTSCB + 4
PTSSRC PTSCB + 2
Figure 5-13. PTS Control Block – Block Transfer Mode
0 0 0
PTS Block Size
PTS Destination Address (high byte)
PTS Destination Address (low byte)
PTS Source Address (high byte)
PTS Source Address (low byte)
M1 M0 BW
Consecutive Block Transfers
PTS Block Size
Specifies the number of bytes or words in each block. Valid values are
1–32, inclusive.
PTS Destination Address
Write the destination memory location to this register. A valid address is
any unreserved memory location within page 00H; however, it must
point to an even address if word transfers are selected.
PTS Source Address
Write the source memory location to this register. A valid address is any
unreserved memory location within page 00H; however, it must point to
an even address if word transfers are selected.
STANDARD AND PTS INTERRUPTS
0 0 0
SU DU SI
Function
0
0
0
8
0
8
0
0
DI
0
5-25