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Name
Type
P2.7:0
I/O
P3.7:0
I/O
P4.7:0
I/O
P5.7:0
I/O
P6.7:0
I/O
PACT#
O
PALE#
I
Table B-4. Signal Descriptions (Continued)
Port 2
This is a standard bidirectional port that is multiplexed with individually
selectable special-function signals.
P2.6 is multiplexed with the ONCE# function. If this pin is held low during reset,
the device will enter ONCE mode, so exercise caution if you use this pin for
input. If you choose to configure this pin as an input, always hold it high during
reset and ensure that your system meets the V
to prevent inadvertent entry into a test mode.
Port 2 is multiplexed as follows: P2.0/TXD/PVER, P2.1/RXD/PALE#,
P2.2/EXTINT/PROG#, P2.3/BREQ#, P2.4/INTOUT#/AINC#, P2.5/HOLD#,
P2.6/HLDA#/ONCE#/CPVER, P2.7/CLKOUT/PACT#.
Port 3
This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs.
The pins are shared with the multiplexed address/data bus, which has comple-
mentary drivers.
P3.7:0 are multiplexed with AD7:0, SLP7:0, and PBUS.7:0.
Port 4
This is an 8-bit, bidirectional, memory-mapped I/O port with open-drain outputs.
The pins are shared with the multiplexed address/data bus, which has comple-
mentary drivers.
P4.7:0 are multiplexed with AD15:8 and PBUS15:8.
Port 5
This is an 8-bit, bidirectional, memory-mapped I/O port.
P5.4 is multiplexed with a special test-mode-entry function. If this pin is held low
during reset, the device will enter a reserved test mode, so exercise caution if
you use this pin for input. If you choose to configure this pin as an input, always
hold it high during reset and ensure that your system meets the V
(see datasheet) to prevent inadvertent entry into a test mode.
Port 5 is multiplexed as follows: P5.0/ALE/ADV#/SLPALE, P5.1/INST/SLPCS#,
P5.2/WR#/WRL#/SLPWR#, P5.3/RD#/SLPRD#, /SLPINT, P5.5/BHE#/WRH#,
P5.6/READY, and P5.7/BUSWIDTH.
Port 6
This is a standard 8-bit bidirectional port.
Port 6 is multiplexed as follows: P6.0/EPA8/COMP0, P6.1/EPA9/COMP1,
P6.2/T1CLK, P6.3/T1DIR, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1.
Programming Active
During auto programming or ROM-dump, a low signal indicates that
programming or dumping is in progress, while a high signal indicates that the
operation is complete.
PACT# is multiplexed with P2.7 and CLKOUT.
Programming ALE
During slave programming, a falling edge causes the device to read a
command and address from the PBUS.
PALE# is multiplexed with P2.1 and RXD.
SIGNAL DESCRIPTIONS
Description
specification (see datasheet)
IH
specification
IH
B-9
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