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Figure 14-18 and Figure 14-19 show sample circuits that use address valid strobe mode. Figure
14-18 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe
mode. This system configuration uses the ADV# signal as both the flash chip-select signal and
the address-latch signal. The lower address lines, AD7:0, are latched because these lines are carry
both address and data information. The upper address lines, AD15:8, are latched only when op-
erating in bus timing modes 1 and 2 because in these modes, the address lines are not driven
throughout the entire bus cycle. (See "Design Considerations" on page 14-39).
RD#
A17:16
AD15:8
8XC196
ADV#
AD7:0
Applies to bus timing modes 1 and 2 only.
A15:8
74AC
373
LE
LE
A7:0
74AC
373
Figure 14-18. 8-bit System with Flash
INTERFACING WITH EXTERNAL MEMORY
OE#
A17:16
A15:8
256K×8
Flash
(28F020)
CS#
D7:0
A7:0
A0291-02
14-31
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