Powerdown Mode; Enabling And Disabling Powerdown Mode - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
The device enters idle mode after executing the IDLPD #1 instruction. Either an interrupt or a
hardware reset will cause the device to exit idle mode. Any enabled interrupt source, either inter-
nal or external, can cause the device to exit idle mode. When an interrupt occurs, the CPU clocks
restart and the CPU executes the corresponding interrupt service or PTS routine. When the routine
is complete, the CPU fetches and then executes the instruction that follows the IDLPD #1 instruc-
tion.
If enabled, the watchdog timer continues to run in idle mode. The device must
be awakened within every 64K state times to clear the WATCHDOG register;
otherwise, the timer will reset the device.
To prevent an accidental return to full power, hold the external interrupt pin
(EXTINT) low while the device is in idle mode.

13.4 POWERDOWN MODE

Powerdown mode places the device into a very low power state by disabling the internal oscilla-
tor and clock generators. Internal logic holds the CPU and peripheral clocks at logic zero, which
causes the CPU to stop executing instructions, the system bus-control signals to become inactive,
the CLKOUT signal to become high, and the peripherals to turn off. Power consumption drops
into the microwatt range (refer to the datasheet for exact specifications). I
leakage. Table B-6 on page B-14 lists the values of the pins during powerdown mode. If V
maintained above the minimum specification, the special-function registers (SFRs) and register
RAM retain their data.

13.4.1 Enabling and Disabling Powerdown Mode

Setting the PD bit in the chip-configuration register 0 (CCR0.0) enables powerdown mode. Clear-
ing it disables powerdown. CCR0 is loaded from the chip configuration byte (CCB0) when the
device is reset.
13-4
NOTE
is reduced to device
CC
is
CC