Intel 8XC196NT User Manual page 463

8XC196NT USER'S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Mnemonic
Length
POP
POPA
POPF
PUSH
PUSHA
PUSHF
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S / L , where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2's complement offset.
A-54
Stack
Direct Immediate
Opcode Length
2 CC —
1 F5 —
1 F3 —
2 C8 3
1 F4 —
1 F2 —
Indirect
(Note 1)
Opcode Length Opcode
— 2 CE
— — —
— — —
C9 2 CA
— — —
— — —
Indexed
(Notes 1, 2)
Length
Opcode
S/L
3/4 CF
— —
— —
3/4 CB
— —
— —