Intel 8XC196NT User Manual page 139

8XC196NT USER'S MANUAL
7. Enable the EPA0 interrupt and select PTS service for it:
— Set INT_MASK.4
— Set PTSSEL.4
8. Enable the interrupts and the PTS. The EI instruction enables interrupts; the EPTS
instruction enables the PTS.
PTS PWM Toggle Mode Control Block
In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM)
output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the
PWM off-time (PTSCONST2), the address pointer (PTSPTR1), and a control register (PTSCON).
PTSCONST2 (H)
PTSCONST2 (L)
PTSCONST1 (H)
PTSCONST1 (L)
PTSPTR1 (H)
PTSPTR1 (L)
PTSCON
Unused
Register Location
PTSCONST2 PTSCB + 6
PTSCONST1 PTSCB + 4
PTSPTR1 PTSCB + 2
Figure 5-16. PTS Control Block – PWM Toggle Mode
5-34
7
7
15
7
15
Pointer 1 Value (high byte)
7
Pointer 1 Value (low byte)
7
M2 M1 M0
7
0 0
PWM Off-time
Write the desired PWM off-time to these bits.
PWM On-time
Write the desired PWM on-time to these bits.
Pointer 1 Value
These bits point to a memory location, usually EPA x _TIME. PTSPTR1
can point to any unreserved memory location within page 00H.
PWM Off-time (high byte)
PWM Off-time (low byte)
PWM On-time (high byte)
PWM On-time (low byte)
— —
0 0 0
Function
0
0
8
0
8
0
0
— TMOD TBIT
0
0 0 0