Chip Configuration Bytes; Special-Function Registers (Sfrs); Memory-Mapped Sfrs - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
4.2.2.6

Chip Configuration Bytes

The chip configuration bytes (CCB0, CCB1, and optionally CCB2) specify the operating envi-
ronment. They specify the bus width, bus-control mode, bus-timing mode, and wait states. They
also control powerdown mode, the watchdog timer, and the operating mode (1-Mbyte or 64-
Kbyte). For the 87C196NT, the CCBs also control OTPROM security and OTPROM remapping.
For the 80C196NT, the CCBs are stored in external memory (locations F2018–F201CH). For the
87C196NT, the CCBs can be stored either in external memory (locations F2018–F201CH) or in
the internal OTPROM (locations FF2018–FF201CH).
The chip configuration bytes are the first bytes fetched from memory when the device leaves the
reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs).
Once they are loaded, the CCRs cannot be changed until the next device reset. Typically, the
CCBs are programmed once when the user program is compiled and are not redefined during nor-
mal operation. "Chip Configuration Registers and Chip Configuration Bytes" on page 14-5 de-
scribes the CCBs and CCRs.
4.2.3

Special-function Registers (SFRs)

The 8XC196NT has both peripheral SFRs and memory-mapped SFRs. The peripheral SFRs are
physically located in the on-chip peripherals. They can be addressed as bytes or as words, and
they can be windowed (see "Windowing" on page 4-15). The memory-mapped SFRs must be ac-
cessed using indirect or indexed addressing modes and cannot be windowed.
Do not use reserved SFRs; write zeros to them or leave them in their default state. When read,
reserved bits and reserved SFRs return undefined values.
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results. External events can change the contents of
SFRs, and some SFRs are cleared when read. For this reason, consider the
implications of using an SFR as an operand in a read-modify-write instruction
(e.g., XORB).
4.2.3.1

Memory-mapped SFRs

Locations 1FE0–1FFFH contain memory-mapped SFRs (Table 4-5). The memory-mapped SFRs
must be accessed from page 00H with indirect or indexed addressing modes, and they cannot be
windowed. If you read a location in this range through a window, the SFR appears to contain
FFH (all ones). If you write a location in this range through a window, the write operation has no
effect on the SFR.
4-8
NOTE