Pwm Signaling; Functional Operation; Figure 14. Duty Cycle Of 20; Figure 15. Duty Cycle Of 50 - Intel Quark D2000 Design Manual

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 Interrupt control per timer:
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5.1

PWM Signaling

The Timer and PWM block supports the generation of PWM Output signals with
configurable low and high times, which allows both the duty cycle and frequency to be
set.
Example PWM Output signals are shown in the following figures.

Figure 14. Duty Cycle of 20%

Figure 15. Duty Cycle of 50%

Figure 16. Duty Cycle of 80%

5.2

Functional Operation

Each counter is identical, has an associated PWM Output, and can be individually
configured with the following options:

Enable
 PWM Mode or Timer Mode
 PWM Duty Cycle and Frequency
 Timer Timeout Period

Interrupt Masking
In PWM Mode, the high and low times can be configured as follows. This assumes a
nominal system clock frequency of 32MHz. The values, in nanoseconds, will differ if the
system clock frequency is changed.
Intel® Quark™ Microcontroller D2000
Platform Design Guide
24
32MHz clock periods (134s)
Interrupt generation on timer expiry
Interrupt mask capability
Pulse Width Modulation (PWM)
November 2016
Document Number: 333580-002EN