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M16C/62P Group (M16C/62P, M16C/62PT)
17.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Tables 17.18 lists the specifications of SIM mode. Table 17.19 lists the registers used in the SIM mode
and the register values set.
Table 17.18 SIM Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
(2)
Generation Timing
Error Detection
NOTES:
1. If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the S2RIC register
does not change.
2. A transmit interrupt request is generated by setting the U2IRS bit to "1" (transmission complete) and U2ERE bit
to "1" (error signal output) in the U2C1 register after reset. Therefore, when using SIM mode, set the IR bit to "0"
(no interrupt request) after setting these bits.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
• Direct format
• Inverse format
• CKDIR bit in U2MR register = 0 (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register
• CKDIR bit = 1 (external clock ) : fEXT/16(n+1)
fEXT: Input from CLK2 pin.
Before transmission can start, the following requirements must be met
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in U2TB register)
Before reception can start, the following requirements must be met
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
(1)
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
(3)
• Framing error
This error occurs when the number of stop bits set is not detected
(3)
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
page 197
f o
3
6
4
Specification
n: Setting value of U2BRG register
17. Serial I/O
00h to FFh
00h to FFh
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