Table of Contents
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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
13.1.3 Special Mode 1 (I
2
I
C bus mode is provided for use as a simplified I
the specifications of the I
mode and the register values set. Table 13.1.3.4 lists the I
the block diagram for I
As shown in Table 13.1.3.2, the microcomputer is placed in I
bits to '010
' and the IICM bit to "1". Because SDA
2
output does not change state until SCL
2
Table 13.1.3.1. I
C bus Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
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. v
2
0 .
0
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e
b
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, 5
2
0
0
7
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E
J
0
9
B
0
2
0
2
0 -
2
0
0
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2 /
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, A
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, B
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2
C bus mode)(UART2)
2
C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I
2
C bus mode. Figure 13.1.3.2 shows SCL
2
• Transfer data length: 8 bits
• During master
The CKDIR bit in the U2MR register is set to "0" (internal clock) : fj/ (2(n+1))
fj = f
, f
, f
1SIO
2SIO
• During slave
The CKDIR bit is set to "1" (external clock) : Input from SCL
• Before transmission can start, the following requirements must be met
_
The TE bit in the U2C1 register is set to "1" (transmission enabled)
_
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
• Before reception can start, the following requirements must be met
_
The RE bit in the U2C1 register is set to "1" (reception enabled)
_
The TE bit in the U2C1 register is set to "1" (transmission enabled)
_
The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
(2)
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be selected
• SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
page 158
f o
3
2
9
C
2 /
6
) T
2
C bus interface compatible mode. Table 13.1.3.1 lists
2
C bus mode fuctions. Figure 13.1.3.1 shows
2
C bus mode by setting the SMD2 to SMD0
transmit output has a delay circuit attached, SDA
2
goes low and remains stably low.
Specification
, f
. n: Setting value in the U2BRG register
8SIO
32SIO
timing.
2
pin
2
13. Serial I/O
2
C bus
00
to FF
16
16
(1)
(1)
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