Special Mode 1 (I 2 C Bus Mode)(Uart2) - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
14.1.3 Special Mode 1 (I
2
I C bus mode is provided for use as a simplified I
specifications of the I
and the register values set. Table 14.13 lists the I
2
diagram for I C bus mode. Figure 14.23 shows SCL
As shown in Table 14.13, the microcomputer is placed in I
to '010 ' and the IICM bit to "1". Because SDA
2
does not change state until SCL
2
Table 14.10 I C bus Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in U2RB register are undefined. The IR bit in the U2RIC register remains
unchanged.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
2
C bus mode)(UART2)
2
C bus mode. Tables 14.11 and 14.12 list the registers used in the I
goes low and remains stably low.
2
• Transfer data length: 8 bits
• During master
the CKDIR bit in the U2MR register is set to "0" (internal clock) : fj/ (2(n+1))
fj = f , f , f
1SIO 2SIO
• During slave
CKDIR bit is set to "1" (external clock ) : Input from SCL
• Before transmission can start, the following requirements must be met
_
The TE bit in the U2C1 register is set to "1" (transmission enabled)
_
The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
• Before reception can start, the following requirements must be met
_
The RE bit in the U2C1 register is set to "1" (reception enabled)
_
The TE bit in the U2C1 register is set to "1" (transmission enabled)
_
The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
(2)
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit in the the next data
• Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be selected
• SDA digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
page 191
f o 3 8 5
2
C interface compatible mode. Table 14.10 lists the
2
C bus mode functions. Figure 14.22 shows the block
timing.
2
2
C bus mode by setting the SMD2 to SMD0 bits
transmit output has a delay circuit attached, SDA output
2
Specification
, f . n: Setting value in the U2BRG register 00
8SIO 32SIO
14. Serial I/O
2
C bus mode
to FF
16 16
pin
2
(1)
(1)