Fujitsu F2MC-16LX MB90F423GA Manuals

Manuals and User Guides for Fujitsu F2MC-16LX MB90F423GA. We have 1 Fujitsu F2MC-16LX MB90F423GA manual available for free PDF download: Hardware Manual

Fujitsu F2MC-16LX MB90F423GA Hardware Manual (724 pages)

16-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Microcontrollers | Size: 6 MB

Table of Contents
9
Chapter 1 Outline
23
Product Outline
24
Features
26
Block Diagram
28
Diagram Showing Package Dimensions
30
Pin Assignment Diagram
32
Description of Pin Functions
34
Types of Input/Output Circuits
38
Precautions for Device Handling
40
Chapter 2 Cpu
43
Outline of CPU
44
Memory Space
46
Memory Map
48
Addressing
50
Addressing with Linear Scheme
51
Addressing with Bank Scheme
52
Allocation of Multiple-Byte Data in the Memory
54
Registers
56
Dedicated Registers
57
Accumulator (A)
59
Stack Pointers (USP, SSP)
62
Processor Status (PS)
64
Program Counter (PC)
68
Direct Page Register (DPR)
69
Bank Registers (PCB, DTB, USB, SSB, ADB)
70
General-Purpose Register
71
Prefix Codes
73
Chapter 3 Interrupts
79
Outline of Interrupts
80
Interrupt Sources and Interrupt Vectors
82
Interrupt Control Registers and Peripheral Functions
85
Interrupt Control Registers (ICR00 to ICR15)
87
Function of Interrupt Control Registers
89
Hardware Interrupts
92
Hardware Interrupt Operation
95
Operation Flow for Hardware Interrupts
97
Procedure for Using Hardware Interrupts
98
Multiple Interrupts
99
Time for Handling Hardware Interrupts
101
Software Interrupts
103
Interrupt by Extended Intelligent I/O Service (EI 2 OS)
105
Extended Intelligent I/O Service (EI 2 OS) Descriptor (ISD)
107
Registers of the Extended Intelligent I/O Service (EI 2 OS) Descriptor (ISD)
109
Operation of the Extended Intelligent I/O Service (EI 2 OS)
112
Procedure for Using the Extended Intelligent I/O Service (EI 2 OS)
113
Processing Time for the Extended Intelligent I/O Service (EI 2 OS)
114
Exception Processing Interrupts When Executing Undefined Instructions
117
Stack Operations of Interrupt Handling
118
Example Program for Interrupt Handling
120
Chapter 4 Reset
125
Outline of Reset Operation
126
Reset Sources and Oscillation Stabilization Wait Time
129
External Reset Pin
131
Reset Operation
132
Reset Source Bit
134
State of each Pin after Reset
138
Chapter 5 Clock
139
Outline of Clock Unit
140
Block Diagram of the Clock Generation Section
143
Clock Selection Register (CKSCR)
145
Clock Mode
148
Oscillation Stabilization Wait Time
152
Connection of Resonator and External Clock
153
Chapter 6 Low-Power Consumption Mode
155
Outline of Low-Power Consumption Mode
156
Block Diagram of Low-Power Consumption Control Circuit
159
Low-Power Consumption Mode Control Register (LPMCR)
161
CPU Intermittent Operation Mode
164
Standby Modes
165
Sleep Mode
166
Timebase Timer Mode
168
Watch Mode
170
Stop Mode
172
State Transition Diagram
174
Pin States in Standby Mode and During Reset
176
Notes on Using the Low-Power Consumption Mode
178
Chapter 7 Mode Settings
183
Setting the Mode
184
Mode Pins (MD2 to MD0)
185
Mode Data
186
Chapter 8 I/O Ports
189
I/O Ports
190
Assignment of Registers and Pins Shared with External Pins
192
Port 0
193
Port 0 Registers (PDR0, DDR0)
195
Description of Port 0 Operation
196
Port 1
198
Port 1 Registers (PDR1, DDR1)
200
Description of Port 1 Operation
201
Port 3
203
Port 3 Registers (PDR3, DDR3)
205
Description of Port 3 Operation
206
Port 4
208
Port 4 Registers (PDR4, DDR4)
210
Description of Port 4 Operation
211
Port 5
213
Port 5 Registers (PDR5, DDR5)
215
Description of Port 5 Operation
216
Port 6
218
Port 6 Registers (PDR6, DDR6, ADER)
220
Description of Port 6 Operation
222
Port 7
224
Port 7 Registers (PDR7, DDR7)
226
Description of Port 7 Operation
227
Port 8
229
Port 8 Registers (PDR8, DDR8)
231
Description of Port 8 Operation
232
Port 9
234
Functions of Port 9 Registers (PDR9, DDR9)
236
Description of Port 9 Operation
237
Example Program for I/O Port
239
Chapter 9 Watchdog Timer/Timebase Timer/Watch Timer (Sub-Clock)
241
Outline of Watchdog Timer/Timebase Timer/Watch Timer
242
Block Diagrams of Watchdog Timer/Timebase Timer/Watch Timer
243
List of Registers for Watchdog Timer/Timebase Timer/Watch Timer
244
Watchdog Timer Control Register (WDTC)
245
Timebase Timer Control Register (TBTC)
247
Watch Timer Control Register (WTC)
249
Operation of Watchdog Timer/Timebase Timer/Watch Timer
251
Watchdog Timer Operation
252
Timebase Timer Operation
254
Watch Timer Operation
256
Notes on Using the Watchdog Timer/Timebase Timer
258
Example Program for Watchdog Timer/Timebase Timer
260
Chapter 10 Input Capture
263
Outline of Input Capture
264
Block Diagram of Input Capture
265
List of Input Capture Registers
266
Detailed Description of the Input Capture Registers
268
Detailed Description of 16-Bit Free-Run Timer Register
270
Description of Operations
275
16-Bit Input Capture
276
16-Bit Free-Run Timer Section
278
Chapter 11 16-Bit Reload Timer
281
Overview of 16-Bit Reload Timer
282
Configuration of 16-Bit Reload Timer
285
Pins of 16-Bit Reload Timer
287
Registers of 16-Bit Reload Timer
289
Upper Bits of Timer Control Status Registers (TMCSR0H/TMCSR1H)
290
Lower Bits of Timer Control Status Registers (TMCSR0L/TMCSR1L)
292
16-Bit Timer Registers (TMR0, TMR1)
294
16-Bit Reload Registers (TMRLR0, TMRLR1)
295
Interrupts of 16-Bit Reload Timer
296
Operation of 16-Bit Reload Timer
297
Internal Clock Mode (Reload Mode)
299
Internal Clock Mode (One-Shot Mode)
301
Event Count Mode
304
Notes on Using the 16-Bit Reload Timer
306
Sample Programs for the 16-Bit Reload Timer
307
Chapter 12 Real-Time Watch Timer
311
Overview of Real-Time Watch Timer
312
Registers of Real-Time Watch Timer
313
Real-Time Watch Timer Control Register
315
Sub-Second Data Register
317
Second/Minute/Hour Data Registers
318
Chapter 13 Ppg Timer
319
Overview of PPG Timer
320
Block Diagram of PPG Timer
322
Registers of PPG Timer
323
Detailed Description of the PPG Timer
324
Operation of PPG Timer
329
Chapter 14 Delay Interrupt Generation Module
333
Overview of Delay Interrupt Generation Module
334
Operation of Delay Interrupt Generation Module
336
Chapter 15 Dtp/External Interrupt Circuit
337
Overview of Dtp/External Interrupt Circuit
338
Configuration of Dtp/External Interrupt Circuit
340
Pins of Dtp/External Interrupt Circuit
342
Registers of Dtp/External Interrupt Circuit
344
Dtp/Interrupt Source Register (EIRR)
345
Dtp/Interrupt Enable Register (ENIR)
346
Request Level Setting Register (ELVRH/ELVRL)
348
Operation of the Dtp/External Interrupt Circuit
350
External Interrupt Function
353
DTP Function
354
Notes on Using the Dtp/External Interrupt Circuit
356
Sample Programs for the Dtp/External Interrupt Circuit
358
Chapter 16 8/10-Bit A/D Converter
361
Overview of 8/10-Bit A/D Converter
362
Configuration of 8/10-Bit A/D Converter
364
Pins of 8/10-Bit A/D Converter
366
Registers of 8/10-Bit A/D Converter
368
Upper Bits of A/D Control Status Register (ADCSH)
369
Lower Bits of A/D Control Status Register (ADCSL)
372
A/D Data Registers (ADCRH/ADCRL)
375
Interrupts of 8/10-Bit A/D Converter
377
Operation of 8/10-Bit A/D Converter
378
Conversion Operation Using EI2OS
380
A/D Conversion Data Protect Function
381
Notes on Using the 8/10-Bit A/D Converter
383
Sample Program 1 for the 8/10-Bit A/D Converter (Example of EI 2 os Start in Single Mode)
384
Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI os Start in Continuous Mode)
386
Sample Program 3 for the 8/10-Bit A/D Converter (Example of EI os Start in Stop Mode)
389
Chapter 17 Uart
391
Overview of UART
392
Configuration of UART
394
Pins of UART
397
Registers of UART
399
Control Registers (SCR0/SCR1)
400
Mode Registers (SMR0/SMR1)
403
Status Registers (SSR0/SSR1)
405
Input Data Registers (SIDR0/SIDR1) and Output Data Registers (SODR0/SODR1)
407
Communication Prescaler Control Registers (CDCR0/CDCR1)
409
Interrupts of UART
411
Timing of Receive Interrupt Generation and Flag Setting
413
Timing of Send Interrupt Generation and Flag Setting
414
Baud Rates of UART
415
Baud Rate Selection by Dedicated Baud Rate Generator
417
Baud Rate Selection by Internal Timer (16-Bit Reload Timer)
420
Baud Rate Selection by External Clock
422
Operation of UART
423
Asynchronous Mode Operation (Operation Modes 0, 1)
425
Synchronous Mode Operation (Operation Mode 2)
428
Bi-Directional Communication Function (Normal Mode)
430
Function for Master/Slave Communication (Multiprocessor Mode)
432
Notes on Using UART
435
Sample Program for UART
436
Chapter 18 Can Controller
439
CAN Controller Features
440
Block Diagram of CAN Controller
441
Types of CAN Controller Registers
442
Control Status Register (CSR)
451
Last Event Indication Register (LEIR)
456
Receive and Transmit Error Counter (RTEC)
458
Bit Timing Register (BTR)
459
Message Buffer Valid Register (BVALR)
462
IDE Register (IDER)
463
Transmission Request Register (TREQR)
464
Transmission RTR Register (TRTRR)
465
Remote Frame Receive Wait Register (RFWTR)
466
Transmission Cancel Register (TCANR)
467
Transmission Complete Register (TCR)
468
Transmission Interrupt Enable Register (TIER)
469
Receive Complete Register (RCR)
470
Remote Request Transmission Register (RRTRR)
471
Receive Overrun Register (ROVRR)
472
Receive Interrupt Enable Register (RIER)
473
Acceptance Mask Selection Register (AMSR)
474
Acceptance Mask Registers 0/1 (AMR0/AMR1)
476
Message Buffers
478
ID Register X (X = 0 to 15) (Idrx)
479
DLC Register X (X = 0 to 15) (Dlcrx)
482
Data Register X (X = 0 to 15) (Dtrx)
483
CAN Wake-Up Control Register (CWUCR)
485
Transmission Via CAN Controller
486
Reception Via CAN Controller
489
Notes on Using CAN Controller
493
Transmission Via Message Buffer (X)
494
Reception Via Message Buffer (X)
496
Specifying the Multi-Level Message Buffer Configuration
498
CAN Wake-Up Function
501
Precautions When Using CAN Controller
503
Sample Program for CAN Controller
504
Chapter 19 Lcd Controller/Driver
507
Outline of LCD Controller/Driver
508
Configuration of LCD Controller/Driver
509
LCD Controller/Driver's Internal Divide Resistor
511
LCD Controller/Driver's External Divide Resistor
513
LCD Controller/Driver Pins
515
LCD Controller/Driver Register
517
Lower Bits of LCD Control Register (LCRL)
518
Upper Bits of LCD Control Register (LCRH)
520
LCD Controller/Driver Display RAM
522
Operation of LCD Controller/Driver
524
Output Waveform During LCD Controller/Driver Operation (1/2 Duty)
526
Output Waveform in LCD Controller/Driver Operation (1/3 Duty)
529
Output Waveform in LCD Controller/Driver Operation (1/4 Duty)
532
Chapter 20 Low-Voltage/Cpu Operation Detection Reset Circuit
535
Outline of the Low-Voltage/Cpu Operation Detection Reset Circuit
536
Configuration of the Low-Voltage/Cpu Operation Detection Reset Circuit
538
Registers of the Low-Voltage/Cpu Operation Detection Reset Circuit
540
Operation of the Low-Voltage/Cpu Operation Detection Reset Circuit
542
Notes on Using the Low-Voltage/Cpu Operation Detection Reset Circuit
543
Sample Program for the Low-Voltage/Cpu Operation Detection Reset Circuit
544
Chapter 21 Stepping Motor Controller
545
Outline of the Stepping Motor Controller
546
Registers of the Stepping Motor Controller
547
PWM Control Register (PWC0 to PWC3)
549
PWM1 and PWM2 Compare Registers (PWC10 to PWC13, PWC20 to PWC23)
550
PWM1/PWM2 Selection Registers (PWS10 to PWS13, PWS20 to PWS23)
552
Operation of the Stepping Motor Controller
554
Notes on Using the Stepping Motor Controller
556
Chapter 22 Sound Generator
557
Outline of the Sound Generator
558
Registers of the Sound Generator
559
Sound Control Register (SGCRH, SGCRL)
560
Frequency Data Register (SGFR)
562
Amplitude Data Register (SGAR)
563
Decrement Grade Register (SGDR)
564
Tone Count Register (SGTR)
565
Chapter 23 Address Match Detection Function
567
Outline of the Address Match Detection Function
568
Example Application of the Address Match Detection Function
571
Example of Program Error Correction
573
Example of Correction Processing
574
Chapter 24 Rom Mirror Function Selection Module
577
Outline of the ROM Mirror Function Selection Module
578
ROM Mirror Function Selection Register (ROMM)
579
Chapter 25 1M Bit Flash Memory
581
Outline of 1M Bit Flash Memory
582
Overall Block Diagram of the Flash Memory and Its Sector Configuration
584
Write/Erase Mode
586
Flash Memory Control Status Register (FMCS)
588
Starting the Flash Memory Automatic Algorithm
590
Confirming the Execution State of the Automatic Algorithm
591
Data Polling Flag (DQ7)
593
Toggle Bit Flag (DQ6)
595
Timing Limit Excess Flag (DQ5)
597
Sector Erasure Timer Flag (DQ3)
598
Detailed Description of Writing/Erasing Flash Memory Data
599
Setting the Flash Memory to Read/Reset State
600
Writing Data to the Flash Memory
601
Erasing All Data in the Flash Memory (Chip Erase)
603
Erasing Data from the Flash Memory (Sector Erase)
604
Suspending Flash Memory Sector Erasure
606
Restarting Flash Memory Sector Erasure
607
Notes on Using Flash Memory
608
Sample Program for the 1M Bit Flash Memory
609
Chapter 26 Example of Serial Programming Connection
613
Basic Configuration
614
Oscillator Clock Frequency and Serial Clock Input Frequency
616
System Configuration of Flash Microcontroller Programmer
617
Examples of Serial Programming Connection
618
Appendix
627
Appendix A I/O Map
628
APPENDIX B Instructions
636
Instruction Types
637
Addressing
638
Direct Addressing
640
Indirect Addressing
646
Execution Cycle Count
654
Effective Address Field
657
How to Read the Instruction List
658
F 2 MC-16LX Instruction List
661
Instruction Map
675
Index
697

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Fujitsu F2MC-16LX MB90F423GA Hardware Manual (724 pages)

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