Bus Status Register (Ibsr) - Fujitsu F2MC-16LX Hardware Manual

22.2.1 Bus Status Register (IBSR)

This section describes the configuration and functions of the bus status register
(IBSR).
I Bus status register (IBSR)
The diagram below shows the bit configuration of the bus status register (IBSR).
Bus status register
Address: 000088
The functions of bits in the bus status register (IBSR) are described below.
[Bit 7] BB: Bus Busy
This bit is used to indicate the I
0
1
[Bit 6] RSC: Repeated Start Condition
This bit is used to detect a repeated start condition.
0
1
This bit is cleared by setting the INT bit to "0" for addressing in a mode other than slave
mode if a start condition is detected in bus idle state or if a stop condition is detected.
[Bit 5] AL: Arbitration Lost
This bit is used to detect the arbitration lost state.
0
1
Cleared if the INT bit is set to "0".
[Bit 4] LRB: Last Received bit
This bit is an acknowledge storage bit used to store an acknowledgement from the reception
side.
This bit is cleared if a start or stop condition is detected.
7 6
H
BB RSC AL
Read/write
(R) (R)
Initial value
(0) (0)
Stop condition is detected
Start condition is detected (bus is used)
Repeated start condition is not detected
Start condition is detected again when bus is used.
Arbitration lost is not detected.
Arbitration lost is generated in master transfer mode, or the MSS bit is set to "1"
while another system is using the bus.
5 4 3 2 1
LRB TRX AAS GCA FBT
(R) (R) (R) (R) (R)
(0) (0) (0) (0) (0)
2
C bus status.
2
CHAPTER 22 I C INTERFACE
0 Bit number
IBSR
(R)
(0)
427