Data Register (Adcr1 And Adcr0) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 15 A/D CONVERTER

15.2.2 Data Register (ADCR1 and ADCR0)

In the data register (ADCR1 and ADCR0), resolution is selected and machine cycle is
set.
■ Data Registers (ADCR1 and ADCR0)
Higher byte of
the data register
Address:00003F
Read/write
Initial value
Lower byte of
the data register
Address:00003E
H
Read/write
Initial value
Note:
Read values of bit9 and bit8 of ADCR0 and ADCR1 are undefined, and the contents of bit11
to bit15 of ADCR1 are always "0".
[bit15] S10
S10 is the A/D resolution select bit.
converter has not started conversion. The contents of ADCR are undefined if rewritten after
conversion.
Table 15.2-6 Functions of S10
S10
0
1
[bit14 ,bit13] ST1 and ST0 (Sampling time)
The ST1 and ST0 bits set the machine cycle number at sampling.
Table 15.2-7 ST1 and ST0 (Machine Cycle Setting Bits at Sampling)
ST1
0
0
1
1
240
Figure 15.2-3 Data Registers (ADCR1 and ADCR0)
bit
15 14 13
S10 ST1 ST0
H
(W) (W) (W)
(0) (0) (0)
bit 7 6
D7 D6 D5
(R) (R) (R)
(X) (X) (X)
10-bit mode [Initial value]
8-bit mode
ST0 Machine cycle at sampling
0 64 machine cycle
1 Reserved
0 Reserved
1 4096 machine cycle
12 11 10
CT1 CT0
(W) (W) (-)
(0) (1) (-)
5 4 3 2
D4 D3 D2
(R) (R) (R)
(X) (X) (X)
When rewriting the S10 bit, confirm that the A/D
Function
9 8
D9 D8 ADCR1
(R) (R)
(X) (X)
1 0
D1 D0 ADCR0
(R) (R)
(X) (X)
Sampling Time
4µs/machine clock 16 MHz
256µs/machine clock 16 MHz