Output Control Register (Opcr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 15 MULTI-PULSE GENERATOR
15.4.1

Output Control Register (OPCR)

The Output Control Register (OPCR) is a register which enables the write timing
interrupt and flag, position detect interrupt and flag, sets the data transfer method, and
sets the control of the OPT5 to OPT0 and DTTI1 pins.
■ Output Control Upper Register (OPCUR)
Address bit
00008B
H
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
372
Figure 15.4-2 Output Control Upper Register (OPCUR)
15 14 13 12
DTIE DTIF NRSL OPS2
R/W R/W R/W R/W
OPS2
11 10 9 8
OPS1 OPS0 WTIF WTIE
R/W R/W R/W R/W
WTIE
0
1
Write timing interrupt request flag bit
WTIF
0 No valid detected.
1 Valid detected.
OPS1 OPS0
Data transfer from OPDBR0 to OPDR after
0 0 0
OPDBR0 is written by software.
Data transfer from OPDBR to OPDR is triggered
0 0 1
by the16-bit reload timer 0 underflow.
Data transfer from OPDBR to OPDR is triggered
0 1 0
by the position detection input.
Data transfer from OPDBR to OPDR is triggered
by the write signal generated by the 16-bit reload
0 1 1
timer 0 underflow, the 16-bit timer is started by
the positon detection comparison circuit.
Data transfer from OPDBR to OPDR is triggered
by the write signal generated either by the 16-bit
1 0 0
reload timer 0 underflow, or by the position
detection input.
1 0 1 One-shot position dectection or timer underflow.
1 1 0 One-shot position dectection.
One-shot position dectection and timer
1 1 1
underfow.
NRSL
0 DTTI1 input does not go through the noise filter.
1 DTTI1 input goes through the noise filter.
DTIF
0 No valid detected.
1 Valid detected.
DTIE
0
1
Initial value
00000000
B
Write timing interrupt enable bit
Disable interrupt.
Enable interrupt.
Read Write
Clear this bit.
No effect.
Function
Noise filter enable bit
DTTI1 interrupt request flag bit
Read Write
Clear this bit.
No effect.
DTTI1 control enable bit
Disable control by the DTTI1 input.
Enable control by the DTTI1 input.