Fuji Electric FRENIC-HVAC User Manual page 560

Block diagram

Analog input
(12, C1, V2
Internal input
terminal)
signal
12
FSUB1
C1
FSUB2
V2 SV1
PV1
ESV1
Input 1 (U02)
Input 2 (U03)
Input 1
Input 2
Input signal
Input 1
Input 2
Input 1
Input 2
Input 1
Input 2
Input 1
Input 2
Digital input
(X terminal)
X1 SS1
SS2
X2
X3 SS4
X4
SS8
X5
RT1
X6 RT2
BX
X7
M3
Hz2/Hz1
FWD FWD
REV
Internal input signal
output signal
FOUT1
FOUT2
Inverter application
IOUT
processing
VOUT
MV1
Customizable logic
Step 1
Output signal
Cumulative
*1
block
(U01, U04, U05)
S001
Step 2
Cumulative
block
S002
Step 3
Cumulative
*2
block
S003
Step 4
Cumulative
block
S004
Step 5
S005
Cumulative
block
(U77)
Step 14
Cumulative
block
S014
RUN
FAR
FDT
IOL
Inverter sequence
SW88
processing
SW52-2
ID2
RDY
LIFE
PID-ALM
TD1
Internal output signal
6-250
Analog output
(FM terminal)
Internal
FM1
FM2
(U71)
CL01(U81)
(U72)
CL02(U82)
Customizable
logic output
(U73)
signal
CL03(U83)
(U74)
CL04(U84)
CL08(U87)
Digital output
(Y terminal)
Y1
Y2
Y3
Y4
Y5
*1
(U71)
0
Disabled
1
S001
2
S002 CL01
14
S014
*2
(U73)
0
Disabled
1
S001
2
S002
3
S003
4
S004 CL03
14
S014