Samsung S5PC100 User Manual page 1421

VIDEO PROCESSOR
4.3.3 Video Processor Shadow Register Update Enable Control Register (VP_SHADOW_UPDATE, W,
Address = 0xF010_ 0008)
VP_SHADOW_UPDATE
Reserved
VP_SHADOW_UPDATE
4.3.4 Video Processor Input Field ID Control Register (VP_FIELD_ID, R/W, Address = 0xF010_ 000C)
VP_FIELD_ID
Reserved
VP_FILED_ID
4.3.5 Video Processor Operation Mode Control Register (VP_MODE, R/W, Address = 0xF010_ 0010)
VP_MODE
Reserved
LINE_SKIP
MEM_MODE
CROMA_EXPANSION
9.8-12
Bit
[31:1] Reserved, read as zero, do not modify
0 = Shadow registers are not updated at the rising
edge of vertical sync.
1 = Shadow registers are updated and this register
[0] is cleared by H/W at the rising edge of vertical
sync.
(Shadow registers are listed in SHADOW
REGISTER MAP table)
Bit
[31:1] Reserved, read as zero, do not modify
When VP_MODE[2] is set to 'high', this bit shows
current FIELD information. Otherwise, when
VP_MODE[2] is set to 'low', this control the pointer
[0]
of top and bottom field.
0 = Top field
1 = Bottom field
Bit
[31:6] Reserved, read as zero, do not modify
This bit can control DMA operation. If it is set to '1',
DMA skips a line per two line while it reads line
data.
[5]
0 = OFF
1 = ON
0 = Linear Mode
[4]
1 = 2D-Tile Mode
(refer to MFC user's manual)
If it is set to '0', only refer to the chrominance of
TOP filed. But set to '1', it uses the chrominance
both TOP and BOTTOM.
[3]
0 = Using only C_TOP_PTR
1 = Using both C_TOP_PTR and C_BOT_PTR
S5PC100 USER'S MANUAL (REV1.0)
Description
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