Confirming The Automatic Algorithm Execution State - Fujitsu MB96300 series Hardware Manual

CHAPTER 33 FLASH MEMORY
33.6

Confirming the Automatic Algorithm Execution State

Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequences.
■ Hardware sequence flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2.
The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit
exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit-2 flag (DQ2). The hardware sequence
flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase
code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 33.5-1 Command sequence table in
Section 33.5 Starting the Flash Memory Automatic Algorithm). Table 33.6-1 Bit assignments of hardware
sequence flags lists the bit assignments of the hardware sequence flags.
Table 33.6-1 Bit assignments of hardware sequence flags
Hardware sequence flag
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control register
(FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state
returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic
writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition,
the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code
write is valid. The following sections describe each hardware sequence flag separately. Table 33.6-2
Hardware sequence flag functions lists the functions of the hardware sequence flags.
860
Bit No. 7
DQ7
6 5 4
DQ6 DQ5 -
3 2 1
DQ3 DQ2 -
0
-