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21.5 Checking the Automatic Algorithm Execution Status
The flash memory uses hardware for notifying the user of the internal operation status
of flash memory and operation completion so as to perform the operation sequence
for write/erase via the automatic algorithm. This automatic algorithm can use the
following hardware sequence flags to check the operation status of flash memory:
I Ready/Busy signal (RDY/BUSYX)
Besides the hardware sequence flags, the flash memory has the Ready/Busy signal as a means
of notifying the user whether the automatic algorithm is being executed or has terminated. This
Ready/Busy signal is connected to the flash memory interface circuit and can be read as the
RDY bit of the flash memory status register (FLCR). At the rising edge of this signal, an interrupt
request can also be issued to the CPU.
When the read value of the RDY bit is 0, data is being written to, or read from the flash memory.
At this time, flash memory does not accept Write and Erase commands. When the read value of
the RDY bit is 1, the flash memory is in read/write status or in erase operation wait status.
I Hardware sequence flags
At halfword read
At byte read (odd address only)
Note: Word read is inhibited (use only the FR-CPU programming mode).
The value of the hardware sequence flag can be obtained as a data item by reading the
respective flash memory address (an odd address during byte access) during execution of the
automatic algorithm. In this data item, five bits are effective, each is used to indicate the status
of the automatic algorithm.
bit
(At halfword or byte access)
These flags are meaningless in FR-CPU ROM mode. Be sure to execute half word or byte read
only in FR-CPU programming mode.
15
(Undefined)
7
6
5
DPOLL
TOGGLE
TLOVER
CHAPTER 21 FLASH MEMORY
8
7
Hardware sequence flag
7
Hardware sequence flag
4
3
2
SETIMR
TOGGL2
(Undefined)
0
0
1
0
(Undefined) (Undefined)
427
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