Interrupt Control Register (Icr); Table 2.8-2 Assignments Of Interrupt Causes And Interrupt Vectors - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 2 CPU
2.8.2

Interrupt Control Register (ICR)

The interrupt control register, which is provided in the interrupt controller, is used to
set the level for each interrupt request. The ICR is divided to correspond to individual
interrupt causes. The ICR is mapped in the I/O address space and accessed from the
CPU via the bus.
Configuration of Interrupt Control Register (ICR)
The configuration of the interrupt control register (ICR) is shown below:
7
Bit Functions of Interrupt Control Register (ICR)
[bit 4] ICR4
This bit is always 1.
[bit 3 to 0] ICR3 to 0
These four bits correspond to the four low-order bits of the interrupt level of the
corresponding interrupt cause. The bits can be read and written.
The bits together with bit 4 enable the ICR to specify a value in the range from 16 to 31.
Interrupt Control Register (ICR) Mapping
Table 2.8.2 Assignments of interrupt causes and interrupt vectors

Table 2.8-2 Assignments of Interrupt Causes and Interrupt Vectors

Interrupt Interrupt control register
cause
Number
IRQ00 ICR00
IRQ01 ICR01
IRQ02 ICR02
: :
: :
IRQ45 ICR45
IRQ46 ICR46
IRQ47 ICR47
See Chapter 8, "Interrupt Controller," for more information.
56
6 5 4 3
IC R4 I CR3 IC R 2 IC R1 IC R0
R R/ W
Address
00000400
H
00000401
H
00000402
H
:
:
0000042D
H
0000042E
H
0000042F
H
2 1 0
R /W R/ W R /W
Corresponding interrupt vector
Number
Hexadecimal Decimal
10
H
11
H
12
H
:
:
3D
H
3E
H
3F
H
Initial value
---1 1 1 1 1
Address
16 TBR+3BC
17 TBR+3B8
18 TBR+3B4
: :
: :
61 TBR+308
62 TBR+304
63 TBR+300
H
H
H
H
H
H