Serial Mode Control Register (Smc) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 13 UART
13.4.1

Serial Mode Control Register (SMC)

The serial mode control register (SMC) specifies the parity setting, stop bit length,
operating mode (data length), and synchronous/asynchronous mode, and enables/
disables UART serial clock output and serial data output.
■
Serial Mode Control Register (SMC)
Address bit7
PEN
0028
H
R/W
R/W : Readable/Writable
: Unused
: Initial value
290
Figure 13.4-2 Serial Mode Control Register (SMC)
bit6 bit5 bit4 bit3 bit2
SBL
MC1 MC0 SMDE
R/W R/W R/W R/W
SOE
0
1
SCKE
0
1
SMDE
0
1
MC1
0
0
1
1
SBL
0
1
PEN
0
1
bit1 bit0
Initial value
00000-00
SCKE SOE
R/W R/W
Serial data output enable bit
General-purpose port or 8-bit serial I/O data output pin
UART serial data output pin
Clock output enable bit
General-purpose port or clock input pin for UART/8-bit serial I/O
UART clock output pin
Synchronization mode selection bit
Synchronous transfer mode
Asynchronous transfer mode
Operating mode selection bits
MC0
Operating
Without parity
mode
(PEN = 0)
0 0
1 1
0 2 8+1 bits
1 3
Stop bit length selection bit
2 bits
1 bit
Parity enable bit
Parity disabled
Parity enabled (TD8/TP in the SSD register allows choice of
even/odd.)
B
Data written:
With parity
(PEN = 1)
6 bits
7 bits
7 bits
8 bits
9 bits 8 bits