General Block Diagram Of Mb91F109; Figure 1.2-1 General Block Diagram Of Mb91F109 - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 1 OVERVIEW
1.2

General Block Diagram of MB91F109

Figure 1.2.1 is a general MB91F109 block diagram.
General Block Diagram of MB91F109
RAM 2KB
Bit Search Module
DMAC (8ch)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
EOP0 EOP1 EOP2
X0 X1
RSTX
INT0-INT3
NMIX
AN0-AN3
AVCC AVRH
AVSS AVRL
ATGX
Notes:
• Terminals are represented by the function (some terminals are actually multiplexed).
• When REALOS is used, perform time management using an external interrupt or internal
timer.
6

Figure 1.2-1 General Block Diagram of MB91F109

FR CPU
D-bus(32bit)
32bit
Bus Converter
Clock Control Unit
(Watch Dog Timer)
Interrupt Control Unit
10bit A/D Converter
(4ch)
Reload Timer
(3 ch)
Port
I-bus(16bit)
Harvard
Princeton
Bus Converter
C-bus
(32bit)
16bit
R-bus
(16bit)
UART (3ch)
with Baud Rate Timer
PWM Timer (4ch)
D31-D16
A24-A00
RDX
WR0X-1X
RDY
CLK
Bus Controller
CS0X-5X
BRQ BGRNTX
RAS0
DRAM Controller CS0L CS1L
CS0H CS1H
DW0X
FLASH ROM
254KB
Port 0-B
RAM 2KB
SI0 SI1 SI2
SO0 SO1 SO2
SC0 SC1 SC2
OCPA0-OCPA3
TRG0-3
RAS1
DW1X