Start/Stop Condition Detect Operation - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

16.12 START/STOP Condition Detect Operation

Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The SSC4
to SSC0 bits in the S2D0 register set the START/STOP conditions. The START/STOP condition can be
detected only when the input signal of the SCL
release time, the set-up time, and the hold time (see Table 16.10). The BB flag in the S10 register is set to
"1" when the START condition is detected and it is set to "0" when the STOP condition is detected. The BB
flag set and reset timing varies between standard clock mode and high-speed clock mode. See Table
16.10.
Figure 16.18 Start condition detection timing diagram
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
SCL release time
Setup time
Hold time
BB flag set/reset
time
NOTES:
1. Unit : number of cycle for I
The SSC value is the decimal notation value of the SSC4 to SSC0 btis. Do not set "0" or odd
numbers to the SSC setting. The values in () are examples when the S2D0 register is set to "18
at V = 4 MHz.
IIC
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
S
CL
S
DA
BB flag
S
CL
S
DA
BB flag
Standard clock mode
SSC value + 1 cycle (6.25µs)
SSC value + 1 cycle < 4.0µs (3.25µs)
2
SSC value cycle < 4.0µs (3.0µs)
2
SSC value - 1 +2 cycles (3.375µs)
2
2
C system clock V
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f o 3 8 5
16. MULTI-MASTER I
and SDA met the following conditions: the SCL
MM MM
S release time
CL
Setup Hold
time
time
BB flag
set time
S release time
CL
Setup Hold
time
time
BB flag
reset time
IIC
2
C bus INTERFACE
High-speed clock mode
4 cycles (1.0µs)
2 cycles (0.5µs)
2 cycles (0.5µs)
3.5 cycles (0.875µs)
"
16