Debug Interface Description - Xilinx MicroBlaze Reference Manual

Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont'd)
Trace_MEM_PipeRun
Trace_MB_Halted
Trace_Jump_Hit
Reserved
1. This signal is only used when

Debug Interface Description

The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor
Debug Module (MDM) IP core. The MDM is controlled by the Xilinx System Debugger
(XSDB) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze
processors at the same time. The debug signals are grouped in the DEBUG bus.
The debug interface can be grouped in the DEBUG bus, using either JTAG serial signals (by
setting
C_DEBUG_INTERFACE = 0
C_DEBUG_INTERFACE = 1
It is also possible to use only AXI4-Lite parallel signals (
in an AXI4 bus, in case the MDM is not used. However, this configuration is not supported
by the tools.
Table 3-15 lists the debug signals on MicroBlaze.
Table 3-15: MicroBlaze Debug Signals
Signal Name
Dbg_Clk
Dbg_TDI
Dbg_TDO
Dbg_Reg_En
1
Dbg_Shift
Dbg_Capture
Dbg_Update
1
Debug_Rst
2
Dbg_Trig_In
Dbg_Trig_Ack_In
Dbg_Trig_Out
Dbg_Trig_Ack_Out
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Signal Name
C_INTERCONNECT
) or the AXI4-Lite compatible parallel signals (by setting
). The MDM configuration must also be set accordingly.
Description
JTAG clock from MDM
JTAG TDI from MDM
JTAG TDO to MDM
Debug register enable from MDM
JTAG BSCAN shift signal from MDM
JTAG BSCAN capture signal from MDM
JTAG BSCAN update signal from MDM
Reset signal from MDM, active high. Should
be held for at least 1
Cross trigger event input to MDM
Cross trigger event input acknowledge from
2
MDM
Cross trigger action output from MDM
2
Cross trigger action output acknowledge to
2
MDM
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Chapter 3: MicroBlaze Signal Interface Description
Bus Index Range
3227
3228
3229
3230 to 4095
= 3 (ACE).
C_DEBUG_INTERFACE = 2
clock cycle.
Clk
VHDL Type
std_logic
std_logic
std_logic
) grouped
VHDL Type Kind
std_logic serial in
std_logic serial in
std_logic serial out
std_logic_vector serial in
std_logic serial in
std_logic serial in
std_logic serial in
std_logic input
std_logic_vector output
std_logic_vector input
std_logic_vector input
std_logic_vector output
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