Xilinx MicroBlaze Reference Manual page 73

Reset
When a
Reset
instructions from the reset vector (address 0x0). Both external reset signals are active high
and should be asserted for a minimum of 16 cycles. See
Chapter 3 for more information on the MSR reset value parameters.
Equivalent Pseudocode
←
PC C_BASE_VECTORS + 0x00000000
←
MSR C_RESET_MSR_IE
C_RESET_MSR_DCE << 8 | C_RESET_MSR_EE
←
EAR 0; ESR
←
PID 0; ZPR
Reservation
Hardware Exceptions
MicroBlaze can be configured to trap the following internal error conditions: illegal
instruction, instruction and data bus error, and unaligned access. The divide exception can
only be enabled if the processor is configured with a hardware divider (
When configured with a hardware floating-point unit (
following floating-point specific exceptions: underflow, overflow, float division-by-zero,
invalid operation, and denormalized operand error.
When configured with a hardware memory management unit (MMU), it can also trap the
following memory management specific exceptions: Illegal Instruction Exception, Data
Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, and Instruction
TLB Miss Exception.
A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware
exception vector (address
exception cycle is not executed.
The exception also updates the general purpose register R17 in the following manner:
• For the MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data
TLB Miss Exception, Instruction TLB Miss Exception) the register R17 is loaded with the
appropriate program counter value to re-execute the instruction causing the exception
upon return. The value is adjusted to return to a preceding
exception is caused by an instruction in a branch delay slot, the value is adjusted to
return to the branch instruction, including adjustment for a preceding
if any.
1. Reset input controlled by the debugger using MDM.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
(1)
or occurs, MicroBlaze flushes the pipeline and starts fetching
Debug_Rst
<< 2 | C_RESET_MSR_BIP << 4 | C_RESET_MSR_ICE << 6 |
← ←
0; FSR 0
← ←
0; TLBX 0
←
0
C_BASE_VECTORS
www.xilinx.com
Chapter 2: MicroBlaze Architecture
MicroBlaze Core Configurability in
<< 9 | C_RESET_MSR_EIP << 10
C_USE_FPU>0
+ 0x20). The execution stage instruction in the
IMM
).
C_USE_DIV=1
), it can also trap the
instruction, if any. If the
instruction,
IMM
73
Send Feedback