Xilinx MicroBlaze Reference Manual page 43

With extended data addressing is enabled (parameter
significant bits of PVR8 and PVR9 are read with the MFS instruction, and the most
significant bits with the MFSE instruction.
When physical address extension (PAE) is enabled (parameters
> 32), the 32 least significant bits of PVR6 and PVR7 are read with the MFS
C_ADDR_SIZE
instruction, and the most significant bits with the MFSE instruction.
Table 2-24 through
Table 2-24: Processor Version Register 0 (PVR0)
Bits Name
0 CFG
1 BS
2 DIV
3 MUL
4 FPU
5 EXC
6 ICU
7 DCU
8 MMU
9 BTC
10 ENDI
11 FT
12 SPROT
13 REORD
14:15 Reserved
16:23 MBV
24:31 USR1
Table 2-25: Processor Version Register 1 (PVR1)
Bits Name
0:31 USR2
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Table 2-36 provide bit descriptions and values.
Description
PVR implementation:
0 = Basic, 1 = Full
Use barrel shifter
Use divider
Use hardware multiplier
Use FPU
Use any type of exceptions
Use instruction cache
Use data cache
Use MMU
Use branch target cache
Selected endianness:
Always 1 = Little endian
Implement fault tolerant features
Use stack protection
Implement reorder instructions
MicroBlaze release version code
0x19 = v8.40.b 0x21 = v9.4
0x1B = v9.0 0x22 = v9.5
0x1D = v9.1 0x23 = v9.6
0x1F = v9.2 0x24 = v10.0
0x20 = v9.3
User configured value 1
Description
User configured value 2
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Chapter 2: MicroBlaze Architecture
> 32), the 32 least
C_ADDR_SIZE
= 3 and
C_USE_MMU
Value
Based on
C_PVR
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
C_USE_FPU > 0 (None)
Based on
C_*_EXCEPTION
Also set if C_USE_MMU > 0 (None)
C_USE_ICACHE
C_USE_DCACHE
C_USE_MMU > 0 (None)
C_USE_BRANCH_TARGET_CACHE
C_ENDIANNESS
C_FAULT_TOLERANT
C_USE_STACK_PROTECTION
C_USE_REORDER_INSTR
0
Release Specific
C_PVR_USER1
Value
C_PVR_USER2
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