Xilinx MicroBlaze Reference Manual page 222

bsi Barrel Shift Immediate
rD, rA, IMM
bsrli
bsrai rD, rA, IMM
rD, rA, IMM
bslli
bsefi rD, rA, IMM
bsifi rD, rA, Width
1. Width = IMM
W
0 1 1 0 0 1
0
6
0 1 1 0 0 1
0
6
Description
The first three instructions shift the contents of register rA by the amount specified by IMM and put
the result in register rD.
Barrel Shift Extract Field extracts a bit field from register rA and puts the result in register rD. The bit
field width is specified by IMM
be in the range 1 - 31, and the condition IMM
Barrel Shift Insert Field inserts a bit field from register rA into register rD, modifying the existing value
in register rD. The bit field width is defined by IMM
IMM . The condition IMM
S
The mnemonic bsll sets the S bit (Side bit). If the S bit is set, the barrel shift is done to the left. The
mnemonics bsrl and bsra clear the S bit and the shift is done to the right.
The mnemonic bsra sets the T bit (Type bit). If the T bit is set, the barrel shift performed is
Arithmetical. The mnemonics bsrl and bsll clear the T bit and the shift performed is Logical.
The mnemonic bsefi sets the E bit (Extract bit). In this case the S and T bits are not used.
The mnemonic bsifi sets the I bit (Insert bit). In this case the S and T bits are not used.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Barrel Shift Right Logical Immediate
Barrel Shift Right Arithmetic Immediate
Barrel Shift Left Logical Immediate
, IMM
Barrel Shift Extract Field Immediate
W S
1
, IMM Barrel Shift Insert Field Immediate
S
- IMM + 1
S
rD rA
11
rD rA
11
and the shift amount is specified by IMM
W
≥ IMM must apply.
W S
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Chapter 5: MicroBlaze Instruction Set Architecture
0 0 0 0
0 S T 0 0 0 0
16 21
I E 0 0 0 IMM
16 21
+ IMM ≤ 32 must apply.
W S
- IMM + 1, and the shift amount is specified by
W S
IMM
31
27
0 IMM
W
S
25 31
27
. The bit field width must
S
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