Xilinx MicroBlaze Reference Manual page 24

• The instructions to be modified could already have been fetched prior to modification:
Into the instruction prefetch buffer
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Into the instruction cache, if it is enabled
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Into a stream buffer, if instruction cache stream buffers are used
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Into the instruction cache, and then saved in a victim buffer, if victim buffers are
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used.
To ensure that the modified code is always executed instead of the old unmodified
code, software must handle all these cases.
• If one or more of the instructions to be modified is a branch, and the branch target
cache is used, the branch target address might have been cached.
To avoid using the cached branch target address, software must ensure that the branch
target cache is cleared prior to executing the modified code.
• The modified instructions might not have been written to memory prior to execution:
They might be en-route to memory, in temporary storage in the interconnect or the
-
memory controller.
They might be stored in the data cache, if write-back cache is used.
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They might be saved in a victim buffer, if write-back cache and victim buffers are
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used.
Software must ensure that the modified instructions have been written to memory before
being fetched by the processor.
The annotated code below shows how each of the above issues can be addressed. This code
assumes that both instruction cache and write-back data cache is used. If not, the
corresponding instructions can be omitted.
The following code exemplifies storing a modified instruction:
swi
wdc.flush r6,r0
mbar
wic
mbar
The physical and virtual addresses above are identical, unless MMU virtual mode is used. If
the MMU is enabled, the code sequences must be executed in real mode, because WIC and
WDC are privileged instructions. The first instruction after the code sequences above must
not be modified, because it might have been prefetched.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
r5,r6,0 ; r5 = new instruction
; r6 = physical instruction address
; flush write-back data cache line
1 ; ensure new instruction is written to memory
r7,r0 ; invalidate line, empty stream & victim buffers
; r7 = virtual instruction address
2 ; empty prefetch buffer, clear branch target cache
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Chapter 2: MicroBlaze Architecture
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