Xilinx XAPP169 Application Note

Xilinx inc. mp3 player user manual

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XAPP169 (v1.0) November 24, 1999
Summary
Introduction
MP3
Background
XAPP169 (v1.0) November 24, 1999
R
This application note illustrates the use of Xilinx Spartan-II FPGA and an IDT RC32364 RISC
controller in a handheld, consumer electronics platform. Specifically the target application is an
MP3 audio player with advanced user interface features.
In this application the Spartan device is used to implement the complex system level glue logic
required to interface and manage the memory and I/O devices. The RC32364 implements the
MP3 decoding functions, the graphical user interface, and various device control functions.
While the design is targeted at solving a specific problem, decoding and playing compressed
audio streams, it illustrates solutions to a number of general technical issues. These include:
• Supporting a graphical user interface in an embedded system.
• Implementing cost-effective interfaces to LCD displays, touch screens, USB, IRDA, and
CompactFlash in an embedded system.
• Error handling when using NAND FLASH memory.
• Controlling SDRAM memory.
MP3 Market
The MP3 player market emerged in late 1998, when Diamond Multimedia shipped its Rio MP3
audio player. While there is considerable diversity in opinions about the potential size of this
market, market analysts all agree that the opportunity is significant and will experience rapid
growth in the short term. Like any new market, the feature set of MP3 players is likely to change
as more users buy them. Key dynamics in this market include:
• Copy Protection. While the Secure Digital Music Initiative (SDMI) promises to make a
wider variety of music available in MP3 format, there is considerable technical uncertainty
about implementation timetables.
• Non-MP3 Formats. While MP3 is the dominant format for music available on the Internet,
other large players are pushing other formats tailored to their business agendas.
• Extended Features. At $150 to $250 an MP3 player is a relatively expensive consumer
electronics purchase. The dominant component of that price is the FLASH memory that
these devices use. This cost component is more or less the same for all vendors, and
constrains price point differentiation. One way to increase the perceived value of an MP3
player, and therefore get a competitive advantage, is to add value added features tailored to
the target market.
Due to these market dynamics, including the potential for rapid changes in feature
requirements, the best approach is a flexible high-performance system. This flexibility
manifests itself in two forms. The first is the use of a high-performance processor, which
supports the addition of additional soft features without the need to resort to optimized
assembly language. The second is the use of a low-cost, high-density FPGA to provide flexible
I/O support for the processor.
MP3 NG: A Next Generation Consumer
Platform
Application Note
www.xilinx.com
1-800-255-7778
Application Note: Spartan-II
1

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Summary of Contents for Xilinx XAPP169

  • Page 1 XAPP169 (v1.0) November 24, 1999 Summary This application note illustrates the use of Xilinx Spartan-II FPGA and an IDT RC32364 RISC controller in a handheld, consumer electronics platform. Specifically the target application is an MP3 audio player with advanced user interface features.
  • Page 2 RC32364 are examined, the following gives an overview of the Application Specific Standard Products (ASSPs) that are included in the design. gives an overview of the design. The key features of which are: www.xilinx.com 1-800-255-7778 XAPP169 (v1.0) November 24, 1999...
  • Page 3 (TLB) capable of supporting demand paged virtual memory. In addition, it includes several features that are valuable in an embedded application such as variable sized pages and lockable TLB entries. by the RC32364. XAPP169 (v1.0) November 24, 1999 Serial Data Control Serial Data...
  • Page 4 (Courtesy IDT) www.xilinx.com 1-800-255-7778 2kB D-Cache, 2-set, ) 4-Kbyte pages Offset Offset passed Virtual-to-physical- unchanged translation in TLB physical memory 32-bit Physical Address Offset Virtual-to- Offset unchanged to physical memory. Offset )16-Mbyte pages XAPP169 (v1.0) November 24, 1999 pa ssed...
  • Page 5 The RC32364 interfaces to the system through a 32-bit multiplexed address/data bus. The bus offers a rich set of signals to control transfers of which only a subset was required for this application. XAPP169 (v1.0) November 24, 1999 Figure 4 shows the timing for read transactions on this bus.
  • Page 6 A detailed description of I C specification as described in the references. www.xilinx.com 1-800-255-7778 VQ_HP ANALOG ∆Σ ANALOG VOLUME FILTER CONTROL ANALOG ∆Σ ANALOG VOLUME FILTER CONTROL FILT+ REF_GND C is a multidrop, 2-wire, serial XAPP169 (v1.0) November 24, 1999 VA_HP HEAD- PHONE AMPLIFIER...
  • Page 7 CS4343 documentation as "Serial Audio Format 2". Figure 7 LRCK SCLK SDATA 15 14 13 12 11 10 XAPP169 (v1.0) November 24, 1999 t irs Stop Start t buf t high t hdst...
  • Page 8: Flash Memory

    (512 + 16)Byte x 16384 1st half Page Register & S/A Y-Gating I/O Buffers & Latches Output Global Buffers Driver illustrates the read timing for this device. that is the number valid blocks that XAPP169 (v1.0) November 24, 1999 I/0 0 I/0 7...
  • Page 9 Micron Semiconductor. This device is available in speed grades from 125 to 166 Memory MHz operating over an LVTTL synchronous interface. this device. sheet for the MT48LC1M16 can be found at the following URL: XAPP169 (v1.0) November 24, 1999 Dout N Dout N+1 Page(Row) Address...
  • Page 10 DQML, DQMH DATA OUTPUT REGISTER DATA INPUT REGISTER ACTIVE BANK t AC t AC t OH t OH t OH m + 1 m + 2 m + 3 t HZ t RP XAPP169 (v1.0) November 24, 1999 DQ0- DQ15...
  • Page 11 This mode also reduces the number of interface pins required. For both of these reasons this was chosen for this application. when operating in multiplexed mode. XAPP169 (v1.0) November 24, 1999 shows a block diagram of this device. The complete data sheet for the USBN9602 http://www.national.com/ds/US/USBN9602.pdf...
  • Page 12: System Implementation

    • Management Processes. These modules implement the application levels functions, and these run as processes under the RTOS. RD or WR AD[7:0] ADDR Figure 13: USBN9602 Read / Write Cycle Timing (Courtesy National Semiconductor) www.xilinx.com 1-800-255-7778 DATA Figure 14. The software XAPP169 (v1.0) November 24, 1999...
  • Page 13 Discrete Cosine Transform (DCT) for sub-band synthesis. There are several sources for MP3 decoder code. A fixed point decoder ( splay-0.81- fixpoint.tgz ) that was developed for the Linux ARM project can be downloaded from the following URL: XAPP169 (v1.0) November 24, 1999 Manager RTOS Decoder...
  • Page 14 CPU Interface and the LCD Controller. block diagram of the FPGA. http://www.iis.fhg.de/amm/techinf/layer3/index.html http://www.xaudio.com shows the architecture implemented in the Spartan-II device for this application. It www.xilinx.com 1-800-255-7778 Figure 15 shows a top level XAPP169 (v1.0) November 24, 1999...
  • Page 15 (RD, WR, etc.) control the transfer. The FPGA device resources used to implement this block include an estimated 32 CLBs but no I/O pads. There is no software required to support this block. XAPP169 (v1.0) November 24, 1999 D_OUT[31:0] D_IN[31:0]...
  • Page 16: Cpu Interface

    CPU_ADDR[3:2] CPU_MASTERCLK Bus State Machine CPU_CIP_N CPU_BE_N[3:0] CPU_RD_N CPU_WR_N CPU_ACK_N USB_CS_N USB_RD_N USB_WR_N Figure 16: CPU Interface Block Diagram Table www.xilinx.com 1-800-255-7778 IR_INT_N DAC_INT_N SYS_CLK DIN[31:0] DOUT[31:0] AOUT[31:4] AOUT[3:2] SYS_CLK RD_OUT_N WR_OUT_N[3:0] ACK_IN REQ_OUT GNT_IN XAPP169 (v1.0) November 24, 1999...
  • Page 17: Lcd Controller

    Although the display format cannot be changed in the system, loading different FPGA configurations into the FLASH when the unit is manufactured can accommodate different displays. XAPP169 (v1.0) November 24, 1999 All bus timing is relative to this clock. The CPU core frequency is derived by multiplying this clock.
  • Page 18 X driver data shift clock Output Latch pulse Output Frame signal Output Y driver scan start pulse Output Y driver shift clock www.xilinx.com 1-800-255-7778 Shift DI_D[3:0] Enable Load DI_XSCL DI_LP DI_FR DI_YD DI_YSCL Base Address XAPP169 (v1.0) November 24, 1999...
  • Page 19: Memory Interface

    FPGA build 32-bit words for the CPU reduces the number of bus cycles. This increases performance and also reduces power consumption. XAPP169 (v1.0) November 24, 1999 = X * Y MOD 32 = X * Y REM 32...
  • Page 20: Sdram Controller

    This includes code storage for the CPU as well as storage of the MP3 audio stream. (See (Figure 19) is based on the design developed by Xilinx in SYS_CLK State...
  • Page 21 This not only increases performance but also turns the ECC checking issue into a non real-time software exercise. The estimated FPGA device resources used to implement this block include an estimated 100 CLBs, and the ten I/O pads listed in XAPP169 (v1.0) November 24, 1999 Device decodes from IP Bus Controller...
  • Page 22 Figure 21.) FIFO D_IN[31:0] SYS_CLK INT_N RD_IN_N WR_IN_N[3:0] ACK_N FIFO D_OUT[31:0] Figure 21: IRDA Controller Block Diagram www.xilinx.com 1-800-255-7778 Description Tx State Machine Shift Register IR_TXD Bus State Machine Shift Register IR_RXD Rx State Machine XAPP169 (v1.0) November 24, 1999...
  • Page 23 This hardware consists of two, 4-word FIFOs, one for each audio channel and a state machine to manage the FIFOs and sequence the interface signals. XAPP169 (v1.0) November 24, 1999 Type Output...
  • Page 24: Touch Screen Interface

    C data clock C data Register D_IN[31:0] D_OUT[31:0] Figure 23: Touch Interface Block Diagram Type Description Output Serial data clock Input Serial data in Output Serial data out www.xilinx.com 1-800-255-7778 Description Figure 23 AD_SCK AD_SDI AD_SDO XAPP169 (v1.0) November 24, 1999...
  • Page 25 This design also illustrates how manufacturers can create designs that the optimized integration of an ASIC while supporting the manufacturing and field upgrade flexibility of an FPGA. XAPP169 (v1.0) November 24, 1999 Interface CLB Usage Number of Signals Total: www.xilinx.com...
  • Page 26 References RC32364 RISController, Hardware User’s Manual, April 1999, Integrated Device Technology Xilinx Spartan-II FPGA Data Sheet, January 2000, Xilinx IRMS6100 1.15 Mb/s IrDT Data Transceiver Data Sheet, May 1999, Infineon Technologies SED1743 160-bit LCD Common Driver Data Sheet, Epson Electronics...
  • Page 27: Revision History

    History Date 11/24/99 © 1999 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaim- ers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. XAPP169 (v1.0) November 24, 1999 Version # Initial release.

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