Xilinx MicroBlaze Reference Manual page 33

X-Ref Target - Figure 2-7
0
Table 2-13: Branch Target Register (BTR)
Bits Name
0:31 BTR
Floating-Point Status Register (FSR)
The Floating-Point Status Register contains status bits for the floating-point unit. It can be
read with an MFS, and written with an MTS instruction. When read or written, the register is
specified by setting Sa = 0x0007. The bits in this register are sticky − floating-point
instructions can only set bits in the register, and the only way to clear the register is by
using the MTS instruction. The following figure illustrates the FSR register and
provides bit descriptions and reset values.
X-Ref Target - Figure 2-8
0
Table 2-14: Floating-Point Status Register (FSR)
Bits Name
0:26 Reserved
27 IO
28 DZ
29 OF
30 UF
31 DO
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
BTR
Figure 2-7: BTR
Description
Branch target address used by handler when returning from
an exception caused by an instruction in a delay slot.
Read-only
Reserved
Figure 2-8: FSR
Description
Invalid operation
Divide-by-zero
Overflow
Underflow
Denormalized operand error
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Chapter 2: MicroBlaze Architecture
Reset Value
0x00000000
Table 2-14
28 29
27
OF
IO DZ
Reset Value
undefined
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31
X19744-082517
30 31
UF DO
X19745-091317
0
0
0
0
0
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