Xilinx MicroBlaze Reference Manual page 298

Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
if C_DCACHE_USE_WRITEBACK = 1 then
if T = 1 and EA = 1 then
address
else
address
else if E = 0 then
←
address
else
←
address
if C_DCACHE_LINE_LEN = 4 then
cacheline_mask
cacheline
cacheline_addr
if C_DCACHE_LINE_LEN = 8 then
cacheline_mask
cacheline
cacheline_addr
if C_DCACHE_LINE_LEN = 16 then
cacheline_mask
cacheline
cacheline_addr
if E = 0 and F = 1 and cacheline.Dirty then
=
for i 0 .. C_DCACHE_LINE_LEN - 1 loop
if cacheline.Valid[i] then
Mem(cacheline_addr + i * 4)
if T = 0 then
cacheline.Tag
else if cacheline.Address = cacheline_addr then
cacheline.Tag
if E = 1 then
if F = 1 then
request external cache flush with address
else
request external cache invalidate with address
Registers Altered
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 2 cycles for wdc.clear
• 2 cycles for wdc with
• 3 cycles for wdc with
• 2 + N cycles for wdc.flush, where N is the number of clock cycles required to flush the
cache line to memory when necessary
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
00111
←
(rA) & (rB)
←
(rA) + (rB)
(rA)
(rA) + (rB)
←
(1 << log2(C_DCACHE_BYTE_SIZE) - 4) - 1
←
(DCache Line)[(address >> 4)
← & 0
address xfffffff0
←
(1 << log2(C_DCACHE_BYTE_SIZE) - 5) - 1
←
(DCache Line)[(address >> 5)
← & 0
address xffffffe0
←
(1 << log2(C_DCACHE_BYTE_SIZE) - 6) - 1
←
(DCache Line)[(address >> 6)
← & 0
address xffffffc0
←
0
←
0
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
∧
cacheline_mask]
∧
cacheline_mask]
∧
cacheline_mask]
←
cacheline.Data[i]
=0 or 2
=0
299
Send Feedback