Xilinx MicroBlaze Reference Manual page 108

Table 2-51: Trace Command Register (TCMDR)
Bits Name
3 Clear
2 Start
1 Stop
0 Sample
Trace Status Register
The Trace Status Register (TSR) can be used to determine if trace has been started or not, to
check for cycle count overflow and to read the sampled number of items in the Embedded
Trace Buffer. This register is a read-only register. Issuing a write request to the register does
nothing. See the following figure and table.
X-Ref Target - Figure 2-33
31
Reserved
Table 2-52: Trace Status Register (TSR)
Bits Name
17 Started
16 Overflow
15:0 Item Count
Trace Data Read Register
The Trace Data Read Register (TDRR) contains the oldest item read from the Embedded
Trace Buffer. When the register has been read, the next item is read from the trace buffer. It
is an error to read more items than are available in the trace buffer, as indicated by the item
count in the Trace Status Register. This register is a read-only register. Issuing a write request to
the register does nothing. See the following figure and table.
X-Ref Target - Figure 2-34
31
Reserved
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Clear trace status and empty the trace buffer
Start trace immediately
Stop trace immediately
Sample the number of current items in the trace buffer
18 17 16
STA OF
Figure 2-33: Trace Status Register
Trace started, set to one when trace is started and cleared to zero
when it is stopped
Cycle count overflow, set to one when the cycle count overflows, and
cleared to zero by the Clear command
Sampled trace buffer item count
18 17
Figure 2-34: Trace Data Read Register
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Chapter 2: MicroBlaze Architecture
Description
15
Item Count
Description
Buffer Value
Reset Value
0
0
0
0
0
X19769-082517
Reset Value
0
0
0x0000
0
X19770-082517
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