Debug Interface Description - Xilinx MicroBlaze Reference Manual

Table 3-13: MicroBlaze Lockstep Comparison Signals (Cont'd)
Trace_MB_Halted
Trace_Jump_Hit
Reserved for future use
1. This signal is only used when C_INTERCONNECT = 3 (ACE).

Debug Interface Description

The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor
Debug Module (MDM) IP core. The MDM is controlled by the Xilinx System Debugger
(XSDB) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze
processors at the same time. The debug signals are grouped in the DEBUG bus. The debug
signals on MicroBlaze are listed in
Table 3-14: MicroBlaze Debug Signals
Signal Name
Dbg_Clk
Dbg_TDI
Dbg_TDO
Dbg_Reg_En
1
Dbg_Shift
Dbg_Capture
Dbg_Update
1
Debug_Rst
2
Dbg_Trig_In
Dbg_Trig_Ack_In
Dbg_Trig_Out
Dbg_Trig_Ack_Out
Dbg_Trace_Data
Dbg_Trace_Valid
Dbg_Trace_Ready
Dbg_Trace_Clk
1. Updated for MicroBlaze v7.00: Dbg_Shift added and Debug_Rst included in DEBUG bus
2. Updated for MicroBlaze v9.3: Dbg_Trig signals added to DEBUG bus
3. Updated for MicroBlaze v9.4: External Program Trace signal added to DEBUG bus
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Signal Name
Table
JTAG clock from MDM
JTAG TDI from MDM
JTAG TDO to MDM
Debug register enable from MDM
JTAG BSCAN shift signal from MDM
JTAG BSCAN capture signal from MDM
JTAG BSCAN update signal from MDM
Reset signal from MDM, active high. Should
be held for at least 1
Cross trigger event input to MDM
Cross trigger event input acknowledge from
2
MDM
Cross trigger action output from MDM
2
Cross trigger action output acknowledge to
2
MDM
External Program Trace data output to MDM std_logic_vector output
3
External Program Trace valid to MDM
3
External Program Trace ready from MDM
3
External Program Trace clock from MDM
3
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Chapter 3: MicroBlaze Signal Interface Description
Bus Index Range
3228
3229
3230 to 4095
3-14.
Description
clock cycle.
Clk
VHDL Type
std_logic
std_logic
VHDL Type Direction
std_logic input
std_logic input
std_logic output
std_logic_vector input
std_logic input
std_logic input
std_logic input
std_logic input
std_logic_vector output
std_logic_vector input
std_logic_vector input
std_logic_vector output
std_logic output
std_logic input
std_logic input
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