Performance Monitoring - Xilinx MicroBlaze Reference Manual

Performance Monitoring

With extended debugging, MicroBlaze provides performance monitoring counters to count
various events and to measure latency during program execution. The number of event
counters and latency counters can be configured with
C_DEBUG_LATENCY_COUNTERS
bits with
C_DEBUG_COUNTER_WIDTH
to 32 bits and there are five event counters and one latency counter.
An event counter simply counts the number of times a certain event has occurred, whereas
a latency counter provides the following information:
• Number of times the event has occurred (N)
• The sum of each event latency measured by counting clock cycles from the event starts
until it finishes (ΣL), used to calculate the mean latency
• The sum of each event latency squared (ΣL
deviation
• The minimum, shortest, measured latency for all events (L
• The maximum, longest, measured latency for all events (L
The mean latency (μ) is calculated by the formula:
ΣL
μ
------ -
=
The standard deviation (σ) of the latency is calculated by the formula:
σ
-----------------------------------------
=
Counting can be started or stopped using the Performance Counter Command Register or
by cross trigger events (see
When configuring, reading or writing counters, they are accessed sequentially through the
performance counter registers. After every access the selected counter item is incremented.
All counters are sampled simultaneously for reading using the Performance Counter
Command Register. This can be done while counting, or after counting has been stopped.
When an event counter reaches its maximum value, the overflow status bit is set, and the
external interrupt signal
clearing the counters using the Performance Counter Command Register.
By using one of the event counters to count number of clock cycles, and initializing this
counter to overflow after a predetermined sampling interval, the external interrupt can be
used to periodically sample the performance counters.
The available events are described in
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
respectively, and the counter width can be set to 32, 48 or 64
. With the default configuration, the counter width is set
N
NΣL 2
( ΣL )
2
–
N
Table 2-62).
is set to one. The interrupt signal is reset to zero by
Dbg_Intr
www.xilinx.com
Chapter 2: MicroBlaze Architecture
C_DEBUG_EVENT_COUNTERS
2
), used to calculate the latency standard
Table 2-41, listed in numerical order.
and
)
min
)
max
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