Xilinx MicroBlaze Reference Manual page 50

Three Stage Pipeline
With
C_AREA_OPTIMIZED
minimize hardware cost: Fetch, Decode, and Execute.
instruction 1
instruction 2
instruction 3
The three stage pipeline does not have any data hazards. Pipeline stalls are caused by
control hazards, structural hazards due to multi-cycle instructions, memory accesses using
slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are barrel shift, multiply, divide and floating-point
instructions.
Five Stage Pipeline
With
C_AREA_OPTIMIZED
maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and
Writeback (WB).
cycle1 cycle2 cycle3
instruction 1
instruction 2
instruction 3
The five stage pipeline has two kinds of data hazard:
• An instruction in OF needs the result from an instruction in EX as a source operand. In
this case, the EX instruction categories are load, store, barrel shift, multiply, divide, and
floating-point instructions. This results in a 1-2 cycle stall.
• An instruction in OF uses the result from an instruction in MEM as a source operand. In
this case, the MEM instruction categories are load, multiply, and floating-point
instructions. This results in a 1 cycle stall.
Pipeline stalls are caused by data hazards, control hazards, structural hazards due to multi-
cycle instructions, memory accesses using slower memory, instruction fetch from slower
memory, or stream accesses.
The multi-cycle instruction categories are divide and floating-point instructions.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
set to 1 (Area), the pipeline is divided into three stages to
cycle1 cycle2 cycle3
Fetch Decode Execute
Fetch Decode
Fetch
set to 0 (Performance), the pipeline is divided into five stages to
cycle4
IF OF EX MEM
IF OF
IF
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Chapter 2: MicroBlaze Architecture
cycle4 cycle5 cycle6
Execute Execute Execute
Decode Stall
cycle5 cycle6 cycle7
WB
EX MEM MEM MEM
OF EX Stall Stall
cycle7
Stall Execute
cycle8 cycle9
WB
MEM WB
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