Xilinx MicroBlaze Reference Manual page 100

The debug registers used to configure and control performance monitoring, and to read or
write the event and latency counters, are listed in
the Performance Counter Command register are accessed repeatedly to read or write
information, first for all of the event counters followed by all of the latency counters.
The
DBG_CTRL
Register to access the register, used with MDM software access to debug registers.
Table 2-42: MicroBlaze Performance Monitoring Debug Registers
Register Name
Performance
Counter Control
Performance
Counter Command
Performance
Counter Status
Performance
Counter Data Read
Performance
Counter Data Write
Performance Counter Control Register
The Performance Counter Control Register (PCCTRLR) is used to define the events that are
counted by the configured performance counters. To define the events for all configured
counters, the register should be written repeatedly for each of the counters. This register is
a write-only register. Issuing a read request has no effect, and undefined data is read.
Every time the register is written, the selected counter is incremented. By using the
Performance Counter Command Register, the selected counter can be reset to the first
counter again. See the following figure and table.
X-Ref Target - Figure 2-26
31
Table 2-43: Performance Counter Control Register (PCCTRLR)
Bits Name
7:0 Event
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
value indicates the value to use in the MDM Debug Register Access Control
MDM
Size (bits)
Command
8 0101 0001
5 0101 0010
2 0101 0011
32 0101 0110
32 0101 0111
Reserved
Figure 2-26: Performance Counter Control Register
Performance counter event, according to
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Chapter 2: MicroBlaze Architecture
Table 2-42. All of these registers except
DBG_CTRL
R/W
Value
Select event for each configured
4A207 W
counter, according to
Command to clear counters, start or
4A404 W
stop counting, or sample counters
Read the sampled status for each
4A601 R
configured performance counter
Read the sampled values for each
4AC1F R
configured performance counter
Write initial values for each
4AE1F W
configured performance counter
8 7
Description
Table 2-41.
Description
Table 2-41
0
Event
X19762-082517
Reset Value
0
100
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