Page 1 MicroBlaze Processor Reference Guide 2016.1 UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 2 Updated for Vivado 2014.3 release: 2014.3 • Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1. • Added version 9.4 to MicroBlaze release version code in PVR. • Included description of external program trace, new in version 9.4 04/15/2015 2015.1 Updated for Vivado 2015.1 release:...
Page 3: Table Of Contents
MicroBlaze Core Configurability ........
Page 4 Xilinx Resources ........
Page 5: Chapter 1: Introduction
Chapter 1 Introduction The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is included in the Vivado® release. The document is intended as a guide to the MicroBlaze hardware architecture. Guide Contents This guide contains the following chapters: •...
Page 6: Overview
Chapter 2 MicroBlaze Architecture This chapter contains an overview of MicroBlaze™ features and detailed information on MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit general purpose registers, virtual-memory management, cache software support, and AXI4-Stream interfaces. Overview The MicroBlaze™ embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx®...
Page 7 Chapter 2: MicroBlaze Architecture Features The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design. The fixed feature set of the processor includes: • Thirty-two 32-bit general purpose registers •...
Page 8 Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version MicroBlaze versions Feature v9.1 v9.2 v9.3 v9.4 v9.5 v9.6 Hardware debug readable ESR and Processor Version Register (PVR) option option option option option option Area or speed optimized...
Page 9 Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version MicroBlaze versions Feature v9.1 v9.2 v9.3 v9.4 v9.5 v9.6 Low-latency interrupt mode option option option option option option Swap instructions option option option option option option Sleep mode and sleep instruction...
Page 10: Data Types And Endianness
The parameter C_ENDIANNESS is fixed to 1 (little-endian). The hardware supported data types for MicroBlaze are word, half word, and byte. When using the reversed load and store instructions LHUR, LWR, SHR and SWR, the bytes in the data are reversed, as indicated by the byte-reversed order.
Page 11: Instructions
Instructions Instruction Summary All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A instructions have up to two source register operands and one destination register operand. Type B instructions have one source register and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an imm instruction).
Page 12 Operation performed on unsigned integer data type float Operation performed on floating point data type clz(r) Count leading zeros Table 2-6: MicroBlaze Instruction Set Summary Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15...
Page 13 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 CMPU Rd,Ra,Rb 000101 00000000011 Rd := Rb + Ra + 1 (unsigned) Rd[0] := 0 if (Rb >= Ra, unsigned) else...
Page 14 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 FCMP.UN Rd,Ra,Rb 010110 01000000000 Rd := 1 if (Rb = NaN or Ra = NaN, float else Rd := 0 FCMP.LT Rd,Ra,Rb...
Page 15 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 AND Rd,Ra,Rb 100001 00000000000 Rd := Ra and Rb XOR Rd,Ra,Rb 00000000000 Rd := Ra xor Rb...
Page 16 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 MTS Sd,Ra 100101 00000 11 & Sd SPR[Sd] := Ra, where: · SPR[0x0001] is MSR · SPR[0x0007] is FSR ·...
Page 17 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRALD Rd,Rb 100110 11100 00000000000 PC := Rb Rd := PC BRK Rd,Rb 100110 01100 00000000000 PC := Rb...
Page 18 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRAID Imm 101110 00000 11000 PC := s(Imm) BRALID Rd,Imm PC := s(Imm) 101110 11100 Rd := PC...
Page 19 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 SBEA Rd,Ra,Rb 110100 00010000000 Addr := Ra & Rb *Addr[0:8] := Rd[24:31] SH Rd,Ra,Rb 110101 00000000000 Addr := Ra + Rb...
Page 20 For a semaphore operation to work properly, the LWX instruction must be paired with an SWX instruction, and both must specify identical addresses. The reservation granularity in MicroBlaze is a word. For both instructions, the address must be word aligned. No unaligned exceptions are generated for these instructions.
Page 21 Chapter 2: MicroBlaze Architecture • Performance can be improved by minimizing looping on an LWX instruction that fails to return a desired value. Performance can also be improved by using an ordinary load instruction to do the initial value check. An implementation of a spinlock exemplifies...
Page 22: Registers
WDC are privileged instructions. The first instruction after the code sequences above must not be modified, since it may have been prefetched. Registers MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to eighteen 32-bit special purpose registers, depending on configured options.
Page 23 0:31 32-bit register used to store return addresses for breaks. 0:31 If MicroBlaze is configured to support hardware exceptions, this register is loaded with the address of the instruction following the instruction causing the HW exception, except for exceptions in delay slots that use BTR instead (see “Branch Target Register...
Page 24 Chapter 2: MicroBlaze Architecture Machine Status Register (MSR) The Machine Status Register contains control and status bits for the processor. It can be read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry copy.
Page 25 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) (Cont’d) Bits Name Description Reset Value User Mode 0 = Privileged Mode, all instructions are allowed 1 = User Mode, certain instructions are not allowed Only available when configured with an MMU (if C_USE_MMU >...
Page 26 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) (Cont’d) Bits Name Description Reset Value Instruction Cache Enable 0 = Instruction Cache disabled 1 = Instruction Cache enabled Only available if configured to use instruction cache C_USE_ICACHE = 1...
Page 27 Chapter 2: MicroBlaze Architecture • An M_AXI_DP exception that specifies the failing AXI4 data access address • A data storage exception that specifies the (virtual) effective address accessed • An instruction storage exception that specifies the (virtual) effective address read •...
Page 28 Chapter 2: MicroBlaze Architecture Table 2-11: Exception Status Register (ESR) Bits Name Description Reset Value 0:18 Reserved Delay Slot Exception. 0 = not caused by delay slot instruction 1 = caused by delay slot instruction Read-only 20:26 Exception Specific Status...
Page 29 TLB miss Branch Target Register (BTR) The Branch Target Register only exists if the MicroBlaze processor is configured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17.
Page 30 Chapter 2: MicroBlaze Architecture ↑ Figure 2-7: BTR Table 2-13: Branch Target Register (BTR) Bits Name Description Reset Value 0:31 Branch target address used by handler when returning from 0x00000000 an exception caused by an instruction in a delay slot.
Page 31 Chapter 2: MicroBlaze Architecture The contents of this register is undefined for all other exceptions. When read with the MFS instruction, the EDR is specified by setting Sa = 0x000D. Figure 2-9 illustrates the EDR register and Table 2-15 provides bit descriptions and reset values.
Page 32 Chapter 2: MicroBlaze Architecture Stack High Register (SHR) The Stack High Register stores the stack high limit use to detect stack underflow. When the address of a load or store instruction using the stack pointer (register R1) as rA is greater than the Stack High Register, a stack underflow occurs, causing a Stack Protection Violation exception if exceptions are enabled in MSR.
Page 33 Zone Protection Register (ZPR) The Zone Protection Register is used to override MMU memory protection defined in TLB entries. It is controlled by the configuration option on MicroBlaze. The register C_USE_MMU is only implemented if is greater than 1 (User Mode),...
Page 34 The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is controlled by the configuration option on C_USE_MMU MicroBlaze. The register is only implemented if is greater than 1 (User Mode), C_USE_MMU is set to 0 (Performance). When accessed with the MFS and MTS C_AREA_OPTIMIZED instructions, the TLBLO is specified by setting Sa = 0x1003.
Page 35 Chapter 2: MicroBlaze Architecture Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO) Bits Name Description Reset Value 0:21 Real Page Number or Physical Page Number 0x000000 When a TLB hit occurs, this field is read from the TLB entry and is used to form the physical address.
Page 36 The Translation Look-Aside Buffer High Register is used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is controlled by the configuration option on C_USE_MMU MicroBlaze. The register is only implemented if is greater than 1 (User Mode), C_USE_MMU is set to 0 (Performance). When accessed with the MFS and MTS C_AREA_OPTIMIZED instructions, the TLBHI is specified by setting Sa = 0x1004.
Page 37 The Translation Look-Aside Buffer Index Register is used as an index to the Unified Translation Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is controlled by the configuration option on MicroBlaze. The register is only C_USE_MMU implemented if...
Page 38 The Translation Look-Aside Buffer Search Index Register is used to search for a virtual page number in the Unified Translation Look-Aside Buffer (UTLB). It is controlled by the configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and is set to 0 (Performance).
Page 39 MSR[PVR]=0. • When is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and C_PVR if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented. When read with the MFS or MFSE instruction the PVR is specified by setting Sa = 0x200x, with x being the register number between 0x0 and 0xB.
Page 40 Chapter 2: MicroBlaze Architecture Table 2-24: Processor Version Register 0 (PVR0) (Cont’d) Bits Name Description Value Use branch target cache C_USE_BRANCH_TARGET_CACHE ENDI Selected endianness: C_ENDIANNESS Always 1 = Little endian Implement fault tolerant features C_FAULT_TOLERANT SPROT Use stack protection C_USE_STACK_PROTECTION...
Page 41 Chapter 2: MicroBlaze Architecture Table 2-26: Processor Version Register 2 (PVR2) (Cont’d) Bits Name Description Value Use msrset and msrclr instructions C_USE_MSR_INSTR PCMP Use pattern compare and CLZ instructions C_USE_PCMP_INSTR AREA Select implementation to optimize area C_AREA_OPTIMIZED = 1 (Area)
Page 42 Chapter 2: MicroBlaze Architecture Table 2-27: Processor Version Register 3 (PVR3) (Cont’d) Bits Name Description Value 25:28 Reserved 29:31 BTC_SIZE Branch Target Cache size C_BRANCH_TARGET_CACHE_SIZE Table 2-28: Processor Version Register 4 (PVR4) Bits Name Description Value Use instruction cache C_USE_ICACHE...
Page 43 Chapter 2: MicroBlaze Architecture Table 2-29: Processor Version Register 5 (PVR5) (Cont’d) Bits Name Description Value Reserved 19:21 DCV Data cache victims 0-3: C_DCACHE_VICTIMS = 0,2,4,8 22:23 Reserved DFTL Data cache tag uses distributed RAM C_DCACHE_FORCE_TAG_LUTRAM DCDW Data cache data width C_DCACHE_DATA_WIDTH >...
Page 44 Chapter 2: MicroBlaze Architecture Table 2-34: Processor Version Register 10 (PVR10) (Cont’d) Bits Name Description Value 8:13 ASIZE Number of extended address bits C_ADDR_SIZE - 32 14:31 Reserved Table 2-35: Processor Version Register 11 (PVR11) Bits Name Description Value Use MMU:...
Page 45: Pipeline Architecture
Chapter 2: MicroBlaze Architecture Pipeline Architecture MicroBlaze instruction execution is pipelined. For most instructions, each stage takes one clock cycle to complete. Consequently, the number of clock cycles necessary for a specific instruction to complete is equal to the number of pipeline stages, and one instruction is completed on every cycle.
Page 46 MicroBlaze supports branches with delay slots. Delay Slots When executing a taken branch with delay slot, only the fetch pipeline stage in MicroBlaze is flushed. The instruction in the decode stage (branch delay slot) is allowed to complete.
Page 47 Chapter 2: MicroBlaze Architecture There are three cases where the branch prediction can cause a mispredict, namely: • A conditional branch that should not have been taken, is actually taken, • A conditional branch that should actually have been taken, is not taken, •...
Page 48: Memory Architecture
The LMB memory address range must not overlap with AXI4 ranges. parameter is always set to little endian. C_ENDIANNESS MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache read hits, except with set to 1 (Area), when data side accesses and data cache...
Page 49 (more if the posted-write buffer in the memory controller is full). The MicroBlaze instruction and data caches can be configured to use 4, 8 or 16 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns.
Page 50: Privileged Instructions
Chapter 2: MicroBlaze Architecture Privileged Instructions The following MicroBlaze instructions are privileged: • (except when explicitly allowed) GETD,PUT,PUTD • • • (except when only the C bit is affected) MSRCLR MSRSET • • RTID RTBD RTED • (except when jumping to physical address...
Page 51 Chapter 2: MicroBlaze Architecture exception handler performs the actual procedure call to the system-service routine on behalf of the application program. The execution environment expected by the system-service routine requires the execution of prologue instructions to set up that environment. Those instructions usually create the block of storage that holds procedural information (the activation record), update and initialize pointers, and save volatile registers (registers the system-service routine uses).
Page 52: Virtual-Memory Management
Chapter 2: MicroBlaze Architecture Virtual-Memory Management Programs running on MicroBlaze use effective addresses to access a flat 4 GB address space. The processor can interpret this address space in one of two ways, depending on the translation mode: • In real mode, effective addresses are used to directly access physical memory •...
Page 53 Chapter 2: MicroBlaze Architecture Real Mode The processor references memory when it fetches an instruction and when it accesses data with a load or store instruction. Programs reference memory locations using a 32-bit effective address calculated by the processor. When real mode is enabled, the physical address is identical to the effective address and the processor uses it to access physical memory.
Page 54 Chapter 2: MicroBlaze Architecture Each address shown in Figure 2-18 contains a page-number field and an offset field. The page number represents the portion of the address translated by the MMU. The offset represents the byte offset into a page and is not translated by the MMU. The virtual address consists of an additional field, called the process ID (PID), which is taken from the PID register (see Process-ID Register, page 33).
Page 55 TLB. Translation Look-Aside Buffer The translation look-aside buffer (TLB) is used by the MicroBlaze MMU for address translation when the processor is running in virtual mode, memory protection, and storage control. Each entry within the TLB contains the information necessary to identify a virtual...
Page 56 Chapter 2: MicroBlaze Architecture • Data Shadow TLB—The DTLB contains data page-translation entries and is fully associative. The page-translation entries stored in the DTLB represent the most-recently accessed data-page translations from the UTLB. The DTLB is used to minimize contention between data translation and UTLB-update operations. The initialization and management of the DTLB is controlled completely by hardware and is transparent to software.
Page 57 Chapter 2: MicroBlaze Architecture TLB Entry Format Figure 2-20 shows the format of a TLB entry. Each TLB entry is 68 bits and is composed of two portions: TLBLO (also referred to as the data entry), and TLBHI (also referred to as the tag entry).
Page 58 Chapter 2: MicroBlaze Architecture Table 2-37: Page-Translation Bit Ranges by Page Size Page SIZE Tag Comparison Physical Page RPN Bits Page Offset Size (TLBHI Field) Bit Range Number Clear to 0 1 KB TAG[0:21] - Address[0:21] Address[22:31] RPN[0:21] 4 KB...
Page 59 MMU are disabled. After system software initializes the UTLB with page-translation entries, management of the MicroBlaze UTLB is usually performed using interrupt handlers running in real mode. MicroBlaze Processor Reference Guide www.xilinx.com...
Page 60 Chapter 2: MicroBlaze Architecture Figure 2-21 diagrams the general process for examining a TLB entry. TLBHI[V]=1 TLB-Entry Miss TLBHI[TID]=0x00 Compare No Match TLB-Entry Miss TLBHI[TID] with PID Match Compare No Match TLBHI[TAG] with EA[EPN] TLB-Entry Miss using TLBHI[SIZE] Match (TLB Hit)
Page 61 Chapter 2: MicroBlaze Architecture • From privileged mode: The TLB entry specifies a read-only page (TLBLO[WR]=0) that is not otherwise ¨ overridden by the zone field (ZPR[Zn]‚ 10 and ZPR[Zn]‚ 11). This applies to store instructions. Instruction-Storage Exception When virtual mode is enabled, (MSR[VM]=1), an instruction-storage exception occurs when access to a page is not permitted for any of the following reasons: •...
Page 62 Chapter 2: MicroBlaze Architecture TLB Access-Protection Controls Each TLB entry controls three types of access: • Process—Processes are protected from unauthorized access by assigning a unique process ID (PID) to each process. When system software starts a user-mode application, it loads the PID for that application into the PID register. As the application executes, memory addresses are translated using only TLB entries with a TID field in Translation Look-Aside Buffer High (TLBHI) that matches the PID.
Page 63 Chapter 2: MicroBlaze Architecture Changing a zone field in the ZPR applies a protection override across all pages in that zone. Without the ZPR, protection changes require individual alterations to each page translation entry within the zone. Unimplemented zones (when <...
Page 64 Solving the above problems in an efficient manner requires keeping track of page accesses and page modifications. MicroBlaze does not track page access and page modification in hardware. Instead, system software can use the TLB-miss exceptions and the data-storage exception to collect this information.
Page 65: Reset, Interrupts, Exceptions, And Break
C_BASE_VECTORS The address range 0x28 to 0x4F is reserved for future software support by Xilinx. Allocating these addresses for user applications is likely to conflict with future releases of SDK support software.
Page 66 Illegal Instruction Exception, Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, and Instruction TLB Miss Exception. A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware exception vector (address + 0x20). The execution stage instruction in the C_BASE_VECTORS exception cycle is not executed.
Page 67 Chapter 2: MicroBlaze Architecture ESR[DS] bit is set. In this case the exception handler should resume execution from the branch target address stored in BTR. The EE and EIP bits in MSR are automatically reverted when executing the instruction. RTED...
Page 68 Chapter 2: MicroBlaze Architecture to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the address. In all other cases the response is ignored. The instructions side local memory (ILMB) can only cause instruction bus exception ¨...
Page 69 Chapter 2: MicroBlaze Architecture • FPU Exception An FPU exception is caused by an underflow, overflow, divide-by-zero, illegal operation, or denormalized operand occurring with a floating point instruction. Underflow occurs when the result is denormalized. ¨ Overflow occurs when the result is not-a-number (NaN).
Page 70 MSR[EE] cleared), the pipeline is halted, and the external signal is set. MB_Error Imprecise Exceptions Normally all exceptions in MicroBlaze are precise, meaning that any instructions in the pipeline after the instruction causing an exception are invalidated, and have no effect. When is set to 1 (...
Page 71 C_BASE_VECTORS Latency The time it takes MicroBlaze to enter a break service routine from the time the break occurs depends on the instruction currently in the execution stage and the latency to the memory storing the break vector.
Page 72 The address of each fast interrupt handler must be passed to the Interrupt Controller when initializing the interrupt system. When a particular interrupt occurs, this address is supplied by the Interrupt Controller, which allows MicroBlaze to directly jump to the handler code. With this mode, MicroBlaze also directly sends the appropriate interrupt acknowledge to...
Page 73 Interrupt_Ack Latency The time it takes MicroBlaze to enter an Interrupt Service Routine (ISR) from the time an interrupt occurs, depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors. If MicroBlaze is configured to have a hardware divider, the largest latency happens when an interrupt occurs during the execution of a division instruction.
Page 74: Instruction Cache
The cacheable instruction address consists of two parts: the cache address, and the tag address. The MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 75 1. This parameter is only available with cache size 8 kB and C_ICACHE_FORCE_TAG_LUTRAM less for 4 word cache-lines, with 16 kB and less for 8 word cache-lines, and with 32 kB and less for 16 word cache-lines. For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000 , and C_ICACHE_HIGHADDR=0x0030ffff...
Page 76 Chapter 2: MicroBlaze Architecture determines the bus data width, either 32 bits, an entire cache line C_ICACHE_DATA_WIDTH (128, 256 or 512 bits), or 512 bits. When is set to 1, a cache miss also occurs if a parity error is detected in C_FAULT_TOLERANT a tag or instruction Block RAM.
Page 77 Chapter 2: MicroBlaze Architecture The contents of the cache are preserved by default when the cache is disabled. You can invalidate cache lines using the WIC instruction or using the hardware debug logic of MicroBlaze. WIC Instruction The optional WIC instruction (...
Page 78: Data Cache
Chapter 2: MicroBlaze Architecture Data Cache Overview MicroBlaze can be used with an optional data cache for improved performance. The cached memory range must not include addresses in the LMB address range. The data cache has the following features: •...
Page 79 The cacheable data address consists of two parts: the cache address, and the tag address. The MicroBlaze data cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 80 Chapter 2: MicroBlaze Architecture With the write-back protocol, a store to an address within the cacheable range always updates the cached data. If the target address word is not in the cache (that is, the access is a cache miss), and the location in the cache contains data that has not yet been written to memory (the cache location is dirty), the old data is written over the data AXI4 interface (M_AXI_DC) to external memory before updating the cache with the new data.
Page 81 ) is used to invalidate or flush cache C_ALLOW_DCACHE_WR=1 lines in the data cache from an application. For a detailed description, please refer to Chapter 5, MicroBlaze Instruction Set Architecture. The WDC instruction can also be used together with parity protection to periodically invalidate entries the cache, to avoid accumulating errors.
Page 82: Floating Point Unit (Fpu)
Chapter 2: MicroBlaze Architecture Floating Point Unit (FPU) Overview The MicroBlaze floating point unit is based on the IEEE 754-1985 standard: • Uses IEEE 754 single precision floating point format, including definitions for infinity, not-a-number (NaN), and zero • Supports addition, subtraction, multiplication, division, comparison, conversion and square root instructions •...
Page 83 Figure 2-24: IEEE 754 Single Precision Format The value of a floating point number v in MicroBlaze has the following interpretation: 1. If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit sign 2.
Page 84 The SDK compiler system, based on GCC, provides support for the Floating Point Unit compliant with the MicroBlaze API. Compiler flags are automatically added to the GCC command line based on the type of FPU present in the system, when using SDK.
Page 85 Chapter 2: MicroBlaze Architecture Libraries and Binary Compatibility The SDK compiler system only includes software floating point C runtime libraries. To take advantage of the hardware FPU, the libraries must be recompiled with the appropriate compiler switches. For all cases where separate compilation is used, it is very important that you ensure the consistency of FPU compiler flags throughout the build.
Page 86 Chapter 2: MicroBlaze Architecture The following “bad” example calculates the sum of squares of the integers from 1 to 10 using floating-point representation: float sum, t; int i; sum = 0.0f; for (i = 1; i <= 10; i++) { t = (float)i;...
Page 87: Stream Link Interfaces
The interfaces on MicroBlaze are 32 bits wide. A separate bit indicates whether the sent/received word is of control or data type. The get instruction in the MicroBlaze ISA is used to transfer information from a port to a general purpose register. The put instruction is used to transfer data in the opposite direction.
Page 88: Debug And Trace
(commonly known as BDM or Background Debug Mode debuggers) like the Xilinx System Debugger (XSDB) tool. The debug interface is designed to be connected to the Xilinx Microprocessor Debug Module (MDM) core, which interfaces with the JTAG port of Xilinx FPGAs.
Page 89 Chapter 2: MicroBlaze Architecture Performance Monitoring With extended debugging, MicroBlaze provides performance monitoring counters to count various events and to measure latency during program execution. The number of event counters and latency counters can be configured with C_DEBUG_EVENT_COUNTERS and C_DEBUG_LATENCY_COUNTERS respectively, and the counter width can be set to 32, 48 or 64 bits with C_DEBUG_COUNTER_WIDTH.
Page 90 Chapter 2: MicroBlaze Architecture A typical procedure to follow when initializing and using the performance monitoring counters is delineated in the steps below. • Initialize the events to be monitored: Use the Performance Command Register (Table 2-43) to reset the selected counter °...
Page 91 Chapter 2: MicroBlaze Architecture Table 2-40: MicroBlaze Performance Monitoring Events Event Description Event Description Event Counter events Any valid instruction executed Floating point (fadd, ..., fsqrt) Load word (lw, lwi, lwx) executed Number of clock cycles Load halfword (lhu, lhui) executed...
Page 92 The DBG_CTRL Value indicates the value to use in the MDM Debug Register Access Control Register to access the register, used with MDM software access to debug registers. Table 2-41: MicroBlaze Performance Monitoring Debug Registers DBG_CTRL Register Name...
Page 93 Chapter 2: MicroBlaze Architecture Performance Counter Command Register The Performance Counter Command Register (PCCMDR) is used to issue commands to clear, start, stop, or sample all counters. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.
Page 94 Chapter 2: MicroBlaze Architecture Table 2-44: Performance Counter Status Register (PCSR) Bits Name Description Reset Value Overflow This bit is set when the counter has counted past its maximum value This bit is set when a new latency counter event is started before the Full previous event has finished.
Page 95 Chapter 2: MicroBlaze Architecture Table 2-46: Performance Counter Data Items (Cont’d) Counter Type Item Description Latency Counter The number of times the event occurred 31:16 0x0000 15:0 The sum of each event latency, 16 most significant bits The sum of each event latency, 32 least significant bits...
Page 96 Chapter 2: MicroBlaze Architecture Program Trace With extended debugging, MicroBlaze provides program trace, either storing information in the Embedded Trace Buffer or transmitting it to the MDM, to enable program execution tracing. The MDM is used when the parameter C_DEBUG_EXTERNAL_TRACE is set, allowing output of program trace from multiple processors via external interfaces.
Page 97 The DBG_CTRL Value indicates the value to use in the MDM Debug Register Access Control Register to access the register, used with MDM software access to debug registers. Table 2-48: MicroBlaze Program Trace Debug Registers DBG_CTRL Register Name Size (bits)
Page 98 Chapter 2: MicroBlaze Architecture Table 2-49: Trace Control Register (TCTRLR) (Cont’d) Bits Name Description Reset Value Save PC Save new program counter for all taken branches Save load and get instruction new data value Save Load Save Return Save new program counter for return instructions...
Page 99 Chapter 2: MicroBlaze Architecture Table 2-51: Trace Status Register (TSR) Bits Name Description Reset Value Trace started, set to one when trace is started and cleared to zero Started when it is stopped Cycle count overflow, set to one when the cycle count overflows, and...
Page 100 Chapter 2: MicroBlaze Architecture Table 2-53: Trace Counter Data Entities (Cont’d) Entity Item Bits Description 17:13 Exception Kind, valid if exception taken Exception taken if set to one Load instruction reading data if set to one Store instruction writing data if set to one...
Page 101 2-54. The DBG_CTRL Value indicates the value to use in the MDM Debug Register Access Control Register to access the register, used with MDM software access to debug registers. Table 2-54: MicroBlaze Profiling Debug Registers DBG_CTRL Register Name Size (bits)
Page 102 Chapter 2: MicroBlaze Architecture Profiling Control Register The Profiling Control Register (PCTRLR) is used to enable (start) profiling and disable (stop) profiling. It is also used to configure whether to count the number of executed instructions or the number of executed clock cycles, as well as define the Profiling Buffer bin usage. This register is a write-only register.
Page 103 Chapter 2: MicroBlaze Architecture Table 2-56: Profiling Low Address Register (PLAR) Bits Name Description Reset Value 29:0 Low word Low word address of the profiled area Profiling High Address Register The Profiling High Address Register (PLAR) is used to define the high word address of the profiled area.
Page 104 Chapter 2: MicroBlaze Architecture Profiling Data Read Register The Profiling Data Read Register (PDRR) reads the bin value indicated by the Profiling Buffer Address Register and increments the Profiling Buffer Address Register. This register is a read- only register. Issuing a write request to the register does nothing.
Page 105 1, MicroBlaze will halt after a few instructions. XSDB DBG_STOP will detect that MicroBlaze has halted, and indicate where the halt occurred. The signal can be used to halt MicroBlaze at any external event, for example when a Vivado integrated logic analyzer is triggered. •...
Page 106 Profiling Control Register or by a cross trigger action. Trace Interface Overview The MicroBlaze trace interface exports a number of internal state signals for performance monitoring and analysis. Xilinx recommends that users only use the trace interface through Xilinx developed analysis cores. This interface is not guaranteed to be backward compatible in future releases of MicroBlaze.
Page 107: Fault Tolerance
It is possible to manually override fault tolerance support in MicroBlaze, by explicitly disabling in the MicroBlaze configuration dialog. This is not C_FAULT_TOLERANT recommended, unless no block RAM is used in MicroBlaze, and there is no need to handle bus exceptions from uncorrectable ECC errors. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 108 Chapter 2: MicroBlaze Architecture Features An overview of all MicroBlaze fault tolerance features is given here. Further details on each feature can be found in the following sections: • “Instruction Cache Operation” • “Data Cache Operation” • “UTLB Management” •...
Page 109 With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface Controller generates error signals on the LMB interface. If exceptions are enabled in MicroBlaze, by setting the EE bit in the Machine Status Register, the uncorrectable error signal either generates an instruction bus exception or a data bus exception, depending on the affected interface.
Page 110 Chapter 2: MicroBlaze Architecture #include "xparameters.h" #include "xtmrctr.h" #include "xintc.h" #include "mb_interface.h" #define SCRUB_PERIOD ... XIntc InterruptController; /* The Interrupt Controller instance */ XTmrCtr TimerCounterInst;/* The Timer Counter instance */ void MicroBlazeScrubHandler(void *CallBackRef, u8 TmrCtrNumber) /* Perform other timer interrupt processing here */ microblaze_scrub();...
Page 111 The standalone BSP BRAM driver is used to access the ECC registers in the LMB BRAM Interface Controller, and also provides a comprehensive self test. By implementing the SDK Xilinx C Project "Peripheral Tests", a self-test example including the BRAM self test for each LMB BRAM Interface Controller in the system is generated.
Page 112 Chapter 2: MicroBlaze Architecture The self-test example can be found in the standalone BSP BRAM driver source code, typically in the subdirectory microblaze_0/libsrc/bram_v3_03_a/src/xbram_selftest.c Scrubbing Scrubbing Methods Scrubbing is performed using specific methods for the different block RAMs: • Instruction and data caches: All lines in the caches are cyclically invalidated using the WIC and WDC instructions respectively.
Page 113 CE_STATUS bit in the ECC Status Register. An interrupt will be generated triggering MicroBlaze to read the failing address and then perform a read followed by a write on the failing address. This will remove the single bit error from the BRAM, thus reducing the risk of the single bit error becoming a uncorrectable double bit error.
Page 114: Lockstep Operation
Chapter 2: MicroBlaze Architecture Lockstep Operation MicroBlaze is able to operate in a lockstep configuration, where two or more identical MicroBlaze cores execute the same program. By comparing the outputs of the cores, any tampering attempts, transient faults or permanent hardware faults can be detected.
Page 115 Chapter 2: MicroBlaze Architecture The outputs from the master MicroBlaze core drive the peripherals in the system. All data leaving the protected area pass through inhibitors. Each inhibitor is controlled from its associated comparator. Each protected area of the design must be implemented in its own partition, using a hierarchical Single Chip Cryptography (SCC) flow.
Page 116 Chapter 2: MicroBlaze Architecture In this system two redundant MicroBlaze processors run in lockstep. A comparator is used to signal an error when a mis-match is detected on the outputs of the two processors. Any error immediately causes both processors to halt, preventing further error propagation.
Page 117: Coherency
• Data Cache invalidation: When a MicroBlaze core in the coherency domain invalidates a data cache line with an external cache invalidation instruction (WDC.EXT.CLEAR or WDC.EXT.FLUSH), hardware messages ensure that all other cores in the coherency domain will do the same. The physical address is always used.
Page 118 Chapter 2: MicroBlaze Architecture After a MicroBlaze core has invalidated one or more entries, it must execute a memory barrier instruction (MBAR), to ensure that all peer processors have completed their TLB invalidation. • Branch Target Cache invalidation: When a MicroBlaze core in the coherency domain invalidates the Branch Target Cache, either with a memory barrier instruction or with a synchronizing branch, hardware messages ensure that all other cores in the coherency domain will do the same.
Page 119 Chapter 2: MicroBlaze Architecture Both interfaces issue the following subset of the possible Distributed Virtual Memory (DVM) transactions: • DVM Operation TLB Invalidate – Hypervisor TLB Invalidate by VA ¨ Branch Predictor Invalidate – Branch Predictor Invalidate all ¨ Physical Instruction Cache Invalidate – Non-secure Physical Instruction Cache ¨...
Page 120: Data Address Extension
Chapter 2: MicroBlaze Architecture Data Address Extension MicroBlaze has the ability to address up to 16EB of data controlled by the parameter C_ADDR_SIZE. This parameter can be set to the following values: NONE 4 * 1024 bytes 32-bit address, no extended address instructions °...
Page 121: Chapter 3: Microblaze Signal Interface Description
MicroBlaze™. Overview The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data and instruction accesses. The following two memory interfaces are supported: Local Memory Bus (LMB), and the AMBA® AXI4 interface (AXI4) and ACE interface (ACE).
Page 122: Microblaze I/O Overview
Chapter 3: MicroBlaze Signal Interface Description MicroBlaze I/O Overview The core interfaces shown in Figure 3-1 and the following Table 3-1 are defined as follows: M_AXI_DP: Peripheral Data Interface, AXI4-Lite or AXI4 interface DLMB: Data interface, Local Memory Bus (BRAM only)
Page 123 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O Signal Interface Description Master Write address ID M_AXI_DP_AWID M_AXI_DP Master Write address M_AXI_DP_AWADDR M_AXI_DP Master Burst length M_AXI_DP_AWLEN M_AXI_DP Master Burst size M_AXI_DP_AWSIZE M_AXI_DP Master Burst type...
Page 124 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Slave Read ID tag M_AXI_DP_RID M_AXI_DP Slave Read data M_AXI_DP_RDATA M_AXI_DP Slave Read response M_AXI_DP_RRESP M_AXI_DP Slave Read last M_AXI_DP_RLAST M_AXI_DP Slave Read valid...
Page 125 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Cache type M_AXI_IP_ARCACHE M_AXI_IP Master Protection type M_AXI_IP_ARPROT M_AXI_IP Master Quality of Service M_AXI_IP_ARQOS M_AXI_IP Master Read address valid M_AXI_IP_ARVALID M_AXI_IP Slave Read address ready...
Page 126 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Slave Response ID M_AXI_DC_BID M_AXI_DC Slave Write response valid M_AXI_DC_BVALID M_AXI_DC Master Response ready M_AXI_DC_BREADY M_AXI_DC Slave Write response user signals M_AXI_DC_BUSER M_AXI_DC...
Page 127 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Snoop ready M_AXI_DC_ACREADY M_ACE_DC Slave Snoop response ready M_AXI_DC_CRREADY M_ACE_DC Master Snoop response valid M_AXI_DC_CRVALID M_ACE_DC Master Snoop response M_AXI_DC_CRRESP M_ACE_DC Master Snoop data valid...
Page 128 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Response ready M_AXI_IC_BREADY M_AXI_IC Slave Write response user signals M_AXI_IC_BUSER M_AXI_IC Slave Write acknowledge M_AXI_IC_WACK M_ACE_IC Master Read address ID M_AXI_IC_ARID M_AXI_IC...
Page 129 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Snoop response valid M_AXI_IC_CRVALID M_ACE_IC Master Snoop response M_AXI_IC_CRRESP M_ACE_IC Master Snoop data valid M_AXI_IC_CDVALID M_ACE_IC Slave Snoop data ready M_AXI_IC_CDREADY M_ACE_IC...
Page 130 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Slave interface input AXI4 channels S0_AXIS.. Sn_AXIS_TLAST S15_AXIS write last Slave interface input AXI4 channels S0_AXIS.. Sn_AXIS_TDATA S15_AXIS write data Slave interface input AXI4 channels S0_AXIS..
Page 131 1. Only used with C_USE_INTERRUPT = 2, for low-latency interrupt support. 2. MicroBlaze is a synchronous design clocked with the Clk signal, except for hardware debug logic, which is clocked with the Dbg_Clk signal. If hardware debug logic is not used, there is no minimum frequency limit for Clk. However, if hardware debug logic is used, there are signals transferred between the two clock regions.
Page 132 To wake up MicroBlaze when in sleep mode, one (or both) of the Wakeup input signals must be set to one. In this case MicroBlaze continues execution after the MBAR instruction.
Page 133 Suspend Hardware Controlled When the Pause input signal is set to one and MicroBlaze has completed all external accesses, the pipeline is halted and the Pause_Ack output signal is set. This indicates to external hardware that it is safe to perform actions such as stopping the clock, resetting the processor or other IP cores.
Page 134: Axi4 And Ace Interface Description
AXI4 and ACE Interface Description Memory Mapped Interfaces Peripheral Interfaces The MicroBlaze AXI4 memory mapped peripheral interfaces are implemented as 32-bit masters. Each of these interfaces only have a single outstanding transaction at any time, and all transactions are completed in order.
Page 135 This interface can have multiple outstanding transactions, either issuing up to 2 transactions when reading, or up to 32 transactions when writing. MicroBlaze ensures that all outstanding writes are completed before a read is issued, since the processor must maintain an ordered memory model but AXI4 or ACE has separate read/write channels without any ordering.
Page 136 Chapter 3: MicroBlaze Signal Interface Description Table 3-4: AXI Memory Mapped Interface Parameters (Cont’d) Interface Parameter Description 32: Default, single word accesses and burst accesses M_AXI_DC C_M_AXI_DC_DATA_WIDTH with C_DCACHE_LINE_LEN word busts used with AXI4 M_ACE_DC and ACE. Write bursts are only used with AXI4 when C_DCACHE_USE_WRITEBACK is set to 1.
Page 137 Chapter 3: MicroBlaze Signal Interface Description Values for access permissions, memory types, quality of service and shareability domain are defined in Table 3-5. Table 3-5: AXI Interface Signal Definitions Interface Signal Description Access Permission: M_AXI_IP C_M_AXI_IP_ARPROT • Unprivileged, secure instruction access (100) if input signal Non_Secure[1] = 0 •...
Page 138 0051A) document for further details. Write Operation A write to the stream interface is performed by MicroBlaze using one of the put or putd instructions. A write operation transfers the register contents to an output AXI4 interface. The transfer is completed in a single clock cycle for blocking mode writes (put and cput instructions) as long as the interface is not busy.
Page 139 Chapter 3: MicroBlaze Signal Interface Description reads as long as data is available. If data is not available, the processor stalls at this instruction until it becomes available. In the non-blocking mode (instructions with prefix n), the transfer is completed in one or two clock cycles irrespective of whether or not data was available.
Page 140: Local Memory Bus (Lmb) Interface Description
Correctable error Uncorrectable error Bus clock 1. N = 32 - 64, set according to parameter C_ADDR_SIZE added in MicroBlaze v9.6. 2. Added in LMB for MicroBlaze v8.00 Addr[0:N-1] The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer.
Page 141 Chapter 3: MicroBlaze Signal Interface Description is valid only in the first clock cycle of the transfer. Valid values for Byte_Enable[0:3] are shown in the following table: Table 3-7: Valid Values for Byte_Enable[0:3] Byte Lanes Used Byte_Enable[0:3] Data[0:7] Data[8:15] Data[16:23] Data[24:31] •...
Page 142 Data_Read[0:31] bus is erroneous, and for byte and halfword writes it indicates that the corresponding data word in local memory was erroneous before writing the new data. All operations on the LMB are synchronous to the MicroBlaze core clock. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 143 Chapter 3: MicroBlaze Signal Interface Description LMB Transactions The following diagrams provide examples of LMB bus operations. Generic Write Operations Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-2: LMB Generic Write Operation, 0 Wait States Addr...
Page 144 Chapter 3: MicroBlaze Signal Interface Description Generic Read Operations Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-4: LMB Generic Read Operation, 0 Wait States Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-5: LMB Generic Read Operation, N Wait States MicroBlaze Processor Reference Guide www.xilinx.com...
Page 145 Chapter 3: MicroBlaze Signal Interface Description Back-to-Back Write Operation Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Don’t Care Don’t Care Figure 3-6: LMB Back-to-Back Write Operation Back-to-Back Read Operation Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care...
Page 146 Chapter 3: MicroBlaze Signal Interface Description Back-to-Back Mixed Write/Read Operation Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-8: Back-to-Back Mixed Write/Read Operation, 0 Wait States Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Don’t Care Don’t Care...
Page 147 • byte transfers to byte devices MicroBlaze does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface. Data steering for read cycles are shown in...
Page 148 Other masters may have more restrictive requirements for byte lane placement than those Note: allowed by MicroBlaze. Slave devices are typically attached “left-justified” with byte devices attached to the most-significant byte lane, and halfword devices attached to the most significant halfword lane.
Page 149: Lockstep Interface Description
Chapter 3: MicroBlaze Signal Interface Description Lockstep Interface Description The lockstep interface on MicroBlaze is designed to connect a master and one or more slave MicroBlaze instances. The lockstep signals on MicroBlaze are listed in Table 3-12. Table 3-12: MicroBlaze Lockstep Signals...
Page 150 Chapter 3: MicroBlaze Signal Interface Description Table 3-13: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type std_logic M_AXI_IP_WLAST std_logic M_AXI_IP_WVALID std_logic M_AXI_IP_BREADY std_logic M_AXI_IP_ARID 374 to 405 std_logic_vector M_AXI_IP_ARADDR 438 to 445 std_logic_vector M_AXI_IP_ARLEN 446 to 448...
Page 151 Chapter 3: MicroBlaze Signal Interface Description Table 3-13: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type std_logic M_AXI_DP_RREADY 723 + n * 35 std_logic Mn_AXIS_TLAST 758 + n * 35 to std_logic_vector Mn_AXIS_TDATA 789 + n * 35...
Page 152 Chapter 3: MicroBlaze Signal Interface Description Table 3-13: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type 2069 to 2070 std_logic_vector M_AXI_IC_ARBAR 2071 std_logic M_AXI_IC_RREADY 2072 std_logic M_AXI_IC_RACK 2073 std_logic M_AXI_IC_ACREADY 2074 std_logic M_AXI_IC_CRVALID 2075 to 2079...
Page 153 Chapter 3: MicroBlaze Signal Interface Description Table 3-13: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type 2857 to 2861 std_logic_vector M_AXI_DC_ARUSER 2862 to 2863 std_logic_vector M_AXI_DC_ARDOMAIN 2864 to 2867 std_logic_vector M_AXI_DC_ARSNOOP 2868 to 2869 std_logic_vector M_AXI_DC_ARBAR...
Page 154: Debug Interface Description
Debug Module (MDM) IP core. The MDM is controlled by the Xilinx System Debugger (XSDB) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the same time. The debug signals are grouped in the DEBUG bus. The debug...
Page 155: Trace Interface Description
It is recommended that you not design custom logic for these signals, but rather to use them via Xilinx provided analysis IP. The trace signals are grouped in the TRACE bus. The current set of trace signals were last updated for MicroBlaze v7.30 and are listed in...
Page 156 Chapter 3: MicroBlaze Signal Interface Description Table 3-15: MicroBlaze Trace Signals (Cont’d) Signal Name Description VHDL Type Direction D-side memory access is a read std_logic output Trace_Data_Read D-side memory access is a write output std_logic Trace_Data_Write Data memory address is within D-...
Page 157 Chapter 3: MicroBlaze Signal Interface Description Table 3-16: Mapping of Trace MSR Trace_MSR_Reg Machine Status Register Name Description Data Cache Enable Division by Zero or Division Overflow Instruction Cache Enable AXI4-Stream Error Break in Progress Arithmetic Carry Interrupt Enable Reserved...
Page 158: Microblaze Core Configurability
Chapter 3: MicroBlaze Signal Interface Description MicroBlaze Core Configurability The MicroBlaze core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements. Configuration is done via parameters that typically enable, size, or select certain processor features.
Page 159 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Generate exception for C_ECC_USE_CE_EXCEPTION integer correctable ECC error Lockstep Slave 0, 1 integer C_LOCKSTEP_SLAVE Disallow FPGA C_AVOID_PRIMITIVES primitives...
Page 160 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Include hardware integer C_USE_FPU floating point unit 0 = None 0, 1, 2 1 = Basic 2 = Extended...
Page 161 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Enable exception integer C_FSL_EXCEPTION handling for Stream Links Generate Bus Error integer C_ECC_USE_CE_EXCEPTION Exceptions for correctable errors Generate exception for...
Page 162 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value External Program Trace integer C_DEBUG_EXTERNAL_TRACE Asynchronous Interrupt integer C_ASYNC_INTERRUPT Asynchronous Wakeup 00,01,10,11 integer C_ASYNC_WAKEUP Level/Edge Interrupt 0, 1...
Page 163 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Instruction cache integer C_ADDR_TAG_BITS 0-25 address tags Instruction cache size 64, 128, 256, integer C_CACHE_BYTE_SIZE 512, 1024, 2048, 4096,...
Page 164 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Memory Management: C_USE_MMU 0 = None 0, 1, 2, 3 1 = User Mode integer 2 = Protection...
Page 165 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Branch Target Cache C_BRANCH_TARGET_CACHE_SIZE size: 0 = Default 1 = 8 entries 2 = 16 entries integer 3 = 32 entries...
Page 166 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Instruction side AXI integer C_M_AXI_IP_SUPPORTS_WRITE support for write accesses Instruction side AXI integer C_M_AXI_IP_SUPPORTS_ narrow burst support NARROW_BURST...
Page 167 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Data cache AXI exclusive integer C_M_AXI_DC_ access support EXCLUSIVE_ACCESS Data cache AXI user integer C_M_AXI_DC_USER_VALUE 0-31 value Instruction cache AXI ID...
Page 168 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: Configuration Parameters (Cont’d) Tool Allowable Default Parameter Name Feature/Description Assign VHDL Type Values Value Select AXI4-Stream integer C_STREAM_INTERCONNECT interconnect AXI4-Stream protocol string GENERIC GENERIC C_Mn_AXIS_PROTOCOL AXI4-Stream protocol string GENERIC GENERIC C_Sn_AXIS_PROTOCOL AXI4-Stream master...
Page 169: Data Types
MicroBlaze Application Binary Interface This chapter describes MicroBlaze™ Application Binary Interface (ABI), which is important for developing software in assembly language for the soft processor. The MicroBlaze GNU compiler follows the conventions described in this document. Any code written by assembly programmers should also follow the same conventions to be compatible with the compiler generated code.
Page 170: Register Usage Conventions
Chapter 4: MicroBlaze Application Binary Interface Register Usage Conventions The register usage convention for MicroBlaze is given in Table 4-2. Table 4-2: Register Usage Conventions Register Type Enforcement Purpose Dedicated Value 0 Dedicated Stack Pointer Dedicated Read-only small data area anchor...
Page 171 Chapter 4: MicroBlaze Application Binary Interface The architecture for MicroBlaze defines 32 general purpose registers (GPRs). These registers are classified as volatile, non-volatile, and dedicated. • The volatile registers (also known as caller-save) are used as temporaries and do not retain values across the function calls.
Page 172: Stack Convention
Chapter 4: MicroBlaze Application Binary Interface Stack Convention The stack conventions used by MicroBlaze are detailed in Table 4-3. The shaded area in Table 4-3 denotes a part of the stack frame for a caller function, while the unshaded area indicates the callee frame function. The ABI conventions of the stack frame define the protocol for passing parameters, preserving non-volatile register values, and allocating space for the local variables in a function.
Page 173 Chapter 4: MicroBlaze Application Binary Interface X-Ref Target - Figure 4-1 High Memory Func 1 Func 1 Func 1 Func 1 Func 2 Func 2 Func 2 Func 3 Low Memory Figure 4-1: Stack Frame Calling Convention The caller function passes parameters to the callee function using either the registers (R5 through R10) or on its own stack frame.
Page 174: Memory Model
8 bytes in the MicroBlaze C compiler (mb-gcc), but this can be changed by giving a command line option to the compiler. Details about this option are discussed in the GNU Compiler Tools chapter.
Page 175: Interrupt, Break And Exception Handling
__attribute__((fast_interrupt)); MicroBlaze allows exception and interrupt handler routines to be located at any address location addressable using 32 bits. The user exception handler code starts with the label _exception_handler, the...
Page 176 _interrupt_handler for interrupts that do not use low-latency handlers. In the current MicroBlaze system, there are dummy routines for interrupt, break and user exception handling, which you can change. In order to override these routines and link your own interrupt and exception handlers, you must define the handler code with specific attributes.
Page 177: Chapter 5: Microblaze Instruction Set Architecture
Chapter 5 MicroBlaze Instruction Set Architecture This chapter provides a detailed guide to the Instruction Set Architecture of MicroBlaze™. Notation The symbols used throughout this chapter are defined in Table 5-1. Table 5-1: Symbol Notation Symbol Meaning Subtract Multiply ×...
Page 178 Chapter 5: MicroBlaze Instruction Set Architecture Table 5-1: Symbol Notation (Cont’d) Symbol Meaning Sign-extend x sext(x) Mem(x) Memory location at address x AXI4-Stream interface x FSLx LSW(x) Least Significant Word of x Floating point: true if x is denormalized isDnz(x) isInfinite(x) Floating point: true if x is +∞...
Page 179: Formats
Instructions This section provides descriptions of MicroBlaze instructions. Instructions are listed in alphabetical order. For each instruction Xilinx provides the mnemonic, encoding, a description, pseudocode of its semantics, and a list of registers that it modifies. MicroBlaze Processor Reference Guide www.xilinx.com...
Page 180 Chapter 5: MicroBlaze Instruction Set Architecture Arithmetic Add rD, rA, rB addc rD, rA, rB Add with Carry addk rD, rA, rB Add and Keep Carry addkc rD, rA, rB Add with Carry and Keep Carry 0 0 0 K C 0...
Page 181 Chapter 5: MicroBlaze Instruction Set Architecture addi Arithmetic Add Immediate addi rD, rA, IMM Add Immediate addic rD, rA, IMM Add Immediate with Carry addik rD, rA, IMM Add Immediate and Keep Carry addikc rD, rA, IMM Add Immediate with Carry and Keep Carry...
Page 182 Chapter 5: MicroBlaze Instruction Set Architecture Logical AND rD, rA, rB 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the contents of register rB; the result is placed into register rD.
Page 183 Chapter 5: MicroBlaze Instruction Set Architecture andi Logial AND with Immediate andi rD, rA, IMM 1 0 1 0 0 1 Description The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the result is placed into register rD.
Page 184 Chapter 5: MicroBlaze Instruction Set Architecture andn Logical AND NOT andn rD, rA, rB 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the logical complement of the contents of register rB;...
Page 185 Chapter 5: MicroBlaze Instruction Set Architecture andni Logical AND NOT with Immediate andni rD, rA, IMM 1 0 1 0 1 1 Description The IMM field is sign-extended to 32 bits. The contents of register rA are ANDed with the logical complement of the extended IMM field;...
Page 186 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Equal rA, rB Branch if Equal beqd rA, rB Branch if Equal with Delay 1 0 0 1 1 1 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is equal to 0, to the instruction located in the offset value of rB.
Page 187 Chapter 5: MicroBlaze Instruction Set Architecture beqi Branch Immediate if Equal beqi rA, IMM Branch Immediate if Equal beqid rA, IMM Branch Immediate if Equal with Delay 1 0 1 1 1 1 D 0 0 0 0 Description Branch if rA is equal to 0, to the instruction located in the offset value of IMM. The target of the branch will be the instruction at address PC + IMM.
Page 188 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater or Equal rA, rB Branch if Greater or Equal bged rA, rB Branch if Greater or Equal with Delay 1 0 0 1 1 1 D 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of rB.
Page 189 Chapter 5: MicroBlaze Instruction Set Architecture bgei Branch Immediate if Greater or Equal bgei rA, IMM Branch Immediate if Greater or Equal bgeid rA, IMM Branch Immediate if Greater or Equal with Delay 1 0 1 1 1 1 D 0 1 0 1 Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of IMM.
Page 190 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater Than rA, rB Branch if Greater Than bgtd rA, rB Branch if Greater Than with Delay 1 0 0 1 1 1 D 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater than 0, to the instruction located in the offset value of rB.
Page 191 Chapter 5: MicroBlaze Instruction Set Architecture bgti Branch Immediate if Greater Than bgti rA, IMM Branch Immediate if Greater Than bgtid rA, IMM Branch Immediate if Greater Than with Delay 1 0 1 1 1 1 D 0 1 0 0 Description Branch if rA is greater than 0, to the instruction located in the offset value of IMM.
Page 192 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less or Equal rA, rB Branch if Less or Equal bled rA, rB Branch if Less or Equal with Delay 1 0 0 1 1 1 D 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB.
Page 193 Chapter 5: MicroBlaze Instruction Set Architecture blei Branch Immediate if Less or Equal blei rA, IMM Branch Immediate if Less or Equal bleid rA, IMM Branch Immediate if Less or Equal with Delay 1 0 1 1 1 1 D 0 0 1 1 Description Branch if rA is less or equal to 0, to the instruction located in the offset value of IMM.
Page 194 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less Than rA, rB Branch if Less Than bltd rA, rB Branch if Less Than with Delay 1 0 0 1 1 1 D 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less than 0, to the instruction located in the offset value of rB.
Page 195 Chapter 5: MicroBlaze Instruction Set Architecture blti Branch Immediate if Less Than blti rA, IMM Branch Immediate if Less Than bltid rA, IMM Branch Immediate if Less Than with Delay 1 0 1 1 1 1 D 0 0 1 0 Description Branch if rA is less than 0, to the instruction located in the offset value of IMM.
Page 196 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Not Equal rA, rB Branch if Not Equal bned rA, rB Branch if Not Equal with Delay 1 0 0 1 1 1 D 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA not equal to 0, to the instruction located in the offset value of rB.
Page 197 Chapter 5: MicroBlaze Instruction Set Architecture bnei Branch Immediate if Not Equal bnei rA, IMM Branch Immediate if Not Equal bneid rA, IMM Branch Immediate if Not Equal with Delay 1 0 1 1 1 1 D 0 0 0 1 Description Branch if rA not equal to 0, to the instruction located in the offset value of IMM.
Page 198 Chapter 5: MicroBlaze Instruction Set Architecture Unconditional Branch Branch Branch Absolute Branch with Delay brad Branch Absolute with Delay brld rD, rB Branch and Link with Delay brald rD, rB Branch Absolute and Link with Delay 1 0 0 1 1 0...
Page 199 Chapter 5: MicroBlaze Instruction Set Architecture Note The instructions brl and bral are not available. A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.
Page 200 As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “bralid rD, C_BASE_VECTORS+0x8“ is used to perform a User Vector Exception, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 201 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • • • MSR[UM], MSR[VM] Latency • 1 cycle (if successful branch prediction occurs) • 2 cycles (if the D bit is set) • 3 cycles (if the D bit is not set, or a branch prediction mispredict occurs) Notes The instructions brli and brali are not available.
Page 202 The BIP flag in the MSR will be set, and the reservation bit will be cleared. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 203 User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs. As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “brki rD, C_BASE_VECTORS+0x8” or “brki rD, C_BASE_VECTORS+0x18” is used to perform a Software Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 204 1 cycle with C_AREA_OPTIMIZED • 2 cycles with C_AREA_OPTIMIZED Note These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions ( C_USE_BARREL =1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 205 Notes These are not Type B Instructions. There is no effect from a preceding imm instruction. These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions ( C_USE_BARREL =1). MicroBlaze Processor Reference Guide www.xilinx.com...
Page 206 Chapter 5: MicroBlaze Instruction Set Architecture Count Leading Zeros rD, rA Count leading zeros in rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Description This instruction counts the number of leading zeros in register rA starting from the most significant bit.
Page 207 Chapter 5: MicroBlaze Instruction Set Architecture Integer Compare rD, rA, rB compare rB with rA (signed) cmpu rD, rA, rB compare rB with rA (unsigned) 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 U 1...
Page 208 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 209 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 210 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 211 28 cycles with =0, 30 cycles with C_AREA_OPTIMIZED C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 212 1 cycle with C_AREA_OPTIMIZED • 3 cycles with C_AREA_OPTIMIZED Note These instructions are only available when the MicroBlaze parameter C_USE_FPU is greater than 0. Table 5-2, page 213 lists the floating point comparison operations. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 213 Chapter 5: MicroBlaze Instruction Set Architecture Table 5-2: Floating Point Comparison Operation Comparison Type Operand Relationship isSigNaN(rA) or isQuietNaN(rA) or Description OpSel (rB) > (rA) (rB) < (rA) (rB) = (rA) isSigNaN(rB) isQuietNaN(rB) Unordered (rD) ← 0 (rD) ← 0 (rD) ←...
Page 214 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 215 5 cycles with C_AREA_OPTIMIZED • 7 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 216 27 cycles with C_AREA_OPTIMIZED • 29 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 217 The get instruction has 32 variants. The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is valid. The non-blocking versions will not stall micro blaze and will set carry to ‘0’ if the data was valid and to ‘1’...
Page 218 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.
Page 219 The getd instruction has 32 variants. The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is valid. The non-blocking versions will not stall micro blaze and will set carry to ‘0’ if the data was valid and to ‘1’...
Page 220 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted. Note The blocking versions of this instruction should not be placed in a delay slot, since this prevents interrupts from being served.
Page 221 • 1 cycle if (rA) = 0, otherwise 35 cycles with C_AREA_OPTIMIZED Note This instruction is only valid if MicroBlaze is configured to use a hardware divider ( C_USE_DIV = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 222 16-bit immediate value field, a 32-bit immediate value cannot be used directly. However, 32- bit immediate values can be used in MicroBlaze. By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction.
Page 223 Chapter 5: MicroBlaze Instruction Set Architecture Load Byte Unsigned rD, rA, rB lbur rD, rA, rB lbuea rD, rA, rB 1 1 0 0 0 0 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a byte (8 bits) from the memory location that results from adding the contents of registers rA and rB.
Page 224 2 cycles with C_AREA_OPTIMIZED Note The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE > 32).
Page 225 Chapter 5: MicroBlaze Instruction Set Architecture lbui Load Byte Unsigned Immediate lbui rD, rA, IMM 1 1 1 0 0 0 Description Loads a byte (8 bits) from the memory location that results from adding the contents of register rA with the value in IMM, sign-extended to 32 bits.
Page 226 Chapter 5: MicroBlaze Instruction Set Architecture Load Halfword Unsigned rD, rA, rB lhur rD, rA, rB lhuea rD, rA, rB 1 1 0 0 0 1 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of registers rA and rB.
Page 227 2 cycles with C_AREA_OPTIMIZED Note The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE > 32).
Page 228 Chapter 5: MicroBlaze Instruction Set Architecture lhui Load Halfword Unsigned Immediate lhui rD, rA, IMM 1 1 1 0 0 1 Description Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of register rA and the value in IMM, sign-extended to 32 bits. The data is placed in the least significant halfword of register rD and the most significant halfword in rD is cleared.
Page 229 Chapter 5: MicroBlaze Instruction Set Architecture Load Word rD, rA, rB rD, rA, rB lwea rD, rA, rB 1 1 0 0 1 0 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of registers rA and rB.
Page 230 2 cycles with C_AREA_OPTIMIZED Note The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE > 32).
Page 231 Chapter 5: MicroBlaze Instruction Set Architecture Load Word Immediate rD, rA, IMM 1 1 1 0 1 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits. The data is placed in register rD.
Page 232 Chapter 5: MicroBlaze Instruction Set Architecture Load Word Exclusive rD, rA, rB 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of registers rA and rB.
Page 233 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • rD and MSR[C], unless an exception is generated, in which case they are unchanged • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated •...
Page 234 MicroBlaze enters sleep mode after all outstanding accesses have been completed. and sets the Sleep, Hibernate or Suspend output signal respectively to indicate this. The pipeline is halted, and MicroBlaze will not continue execution until a bit in the Wakeup input signal is asserted.
Page 235 Chapter 5: MicroBlaze Instruction Set Architecture Move From Special Purpose Register rD, rS mfse rD, rS 1 0 0 1 0 1 0 E 0 0 0 1 0 Description Copies the contents of the special purpose register rS into register rD. The special purpose registers TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.
Page 236 (dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the MFS instruction to guarantee correct FSR value. EAR, ESR and BTR are only valid as operands when at least one of the MicroBlaze C_*_EXCEPTION parameters are set to 1.
Page 237 Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 238 1 are set in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 239 TLBLO and TLBHI are used to copy to the Unified TLB entry indexed by TLBX. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 240 The PC, ESR, EAR, BTR, EDR and PVR0 - PVR12 cannot be written by the MTS instruction. The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0. The SLR and SHR are only valid as a destination if the MicroBlaze parameter is set to 1.
Page 241 3 cycles with C_AREA_OPTIMIZED Note This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 242 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULH is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 243 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 244 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHSU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 245 “imm,” page 222 for details on using 32- bit immediate values. This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016...
Page 246 Chapter 5: MicroBlaze Instruction Set Architecture Logical OR rD, rA, rB 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ORed with the contents of register rB; the result is placed into register rD.
Page 247 Chapter 5: MicroBlaze Instruction Set Architecture Logical OR with Immediate rD, rA, IMM 1 0 1 0 0 0 Description The contents of register rA are ORed with the extended IMM field, sign-extended to 32 bits; the result is placed into register rD.
Page 248 Chapter 5: MicroBlaze Instruction Set Architecture pcmpbf Pattern Compare Byte Find pcmpbf rD, rA, rB bytewise comparison returning position of first match 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is bytewise compared with the contents in register rB.
Page 249 Chapter 5: MicroBlaze Instruction Set Architecture pcmpeq Pattern Compare Equal pcmpeq rD, rA, rB equality comparison with a positive boolean result 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is compared with the contents in register rB.
Page 250 Chapter 5: MicroBlaze Instruction Set Architecture pcmpne Pattern Compare Not Equal pcmpne rD, rA, rB equality comparison with a negative boolean result 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is compared with the contents in register rB.
Page 251 FSLx Description MicroBlaze will write the value from register rA to the link x interface. If the available number of links set by C_FSL_LINKS is less than or equal to FSLx, link 0 is used. The put instruction has 16 variants.
Page 252 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.
Page 253 1 n c t a 0 0 0 0 0 0 Description MicroBlaze will write the value from register rA to the link interface defined by the four least significant bits in rB. If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits in rB, link 0 is used.
Page 254 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted. Note The blocking versions of this instruction should not be placed in a delay slot, since this prevents interrupts from being served.
Page 255 Chapter 5: MicroBlaze Instruction Set Architecture rsub Arithmetic Reverse Subtract rsub rD, rA, rB Subtract rsubc rD, rA, rB Subtract with Carry rsubk rD, rA, rB Subtract and Keep Carry rsubkc rD, rA, rB Subtract with Carry and Keep Carry...
Page 256 Chapter 5: MicroBlaze Instruction Set Architecture rsubi Arithmetic Reverse Subtract Immediate rsubi rD, rA, IMM Subtract Immediate rsubic rD, rA, IMM Subtract Immediate with Carry rsubik rD, rA, IMM Subtract Immediate and Keep Carry rsubikc rD, rA, IMM Subtract Immediate with Carry and Keep Carry...
Page 257 That delay slot instruction has breaks disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 258 That delay slot instruction has interrupts disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 259 This instruction always has a delay slot. The instruction following the RTED is always executed before the branch target. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 260 Chapter 5: MicroBlaze Instruction Set Architecture rtsd Return from Subroutine rtsd rA, IMM 1 0 1 1 0 1 1 0 0 0 0 Description Return from subroutine will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
Page 261 Chapter 5: MicroBlaze Instruction Set Architecture Store Byte rD, rA, rB rD, rA, rB sbea rD, rA, rB 1 1 0 1 0 0 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of registers rA and rB.
Page 262 Chapter 5: MicroBlaze Instruction Set Architecture Note The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE >...
Page 263 Chapter 5: MicroBlaze Instruction Set Architecture Store Byte Immediate rD, rA, IMM 1 1 1 1 0 0 Description Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
Page 264 Chapter 5: MicroBlaze Instruction Set Architecture sext16 Sign Extend Halfword sext16 rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Description This instruction sign-extends a halfword (16 bits) into a word (32 bits). Bit 16 in rA will be copied into bits 0-15 of rD.
Page 265 Chapter 5: MicroBlaze Instruction Set Architecture sext8 Sign Extend Byte sext8 rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Description This instruction sign-extends a byte (8 bits) into a word (32 bits). Bit 24 in rA will be copied into bits 0-23 of rD.
Page 266 Chapter 5: MicroBlaze Instruction Set Architecture Store Halfword rD, rA, rB rD, rA, rB shea rD, rA, rB 1 1 0 1 0 1 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of registers rA and rB.
Page 267 2 cycles with C_AREA_OPTIMIZED Note The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE > 32).
Page 268 Chapter 5: MicroBlaze Instruction Set Architecture Store Halfword Immediate rD, rA, IMM 1 1 1 1 0 1 Description Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of register rA and the value IMM, sign- extended to 32 bits.
Page 269 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right Arithmetic rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Description Shifts arithmetically the contents of register rA, one bit to the right, and places the result in rD.
Page 270 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right with Carry rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Description Shifts the contents of register rA, one bit to the right, and places the result in rD. The Carry flag is shifted in the shift chain and placed in the most significant bit of rD.
Page 271 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right Logical rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 Description Shifts logically the contents of register rA, one bit to the right, and places the result in rD. A zero is shifted in the shift chain and placed in the most significant bit of rD.
Page 272 Chapter 5: MicroBlaze Instruction Set Architecture Store Word rD, rA, rB rD, rA, rB swea rD, rA, rB 1 1 0 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and rB.
Page 273 2 cycles with C_AREA_OPTIMIZED Note The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address ( C_ADDR_SIZE > 32).
Page 274 Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 275 Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions ( C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 276 Chapter 5: MicroBlaze Instruction Set Architecture Store Word Immediate rD, rA, IMM 1 1 1 1 1 0 Description Stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and the value IMM, sign-extended to 32 bits.
Page 277 Chapter 5: MicroBlaze Instruction Set Architecture Store Word Exclusive rD, rA, rB 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Description Conditionally stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and rB.
Page 278 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • MSR[C], unless an exception is generated • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated • ESR[EC], ESR[S], if an exception is generated •...
Page 279 The E bit is only taken into account when the parameter C_INTERCONNECT is set to 3 (ACE). When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) the instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 280 Chapter 5: MicroBlaze Instruction Set Architecture Pseudocode if MSR[UM] = 1 then ← ESR[EC] 00111 else if C_DCACHE_USE_WRITEBACK = 1 then if T = 1 and EA = 1 then ← address (rA) & (rB) else ← address (rA) + (rB) else ←...
Page 281 Chapter 5: MicroBlaze Instruction Set Architecture other cache lines are not inadvertently invalidated, erroneously discarding data that has not yet been written to memory. The address of the affected cache line is always the physical address, independent of the parameter and whether the MMU is in virtual mode or real mode.
Page 282 Register rA contains the address of the affected cache line. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 283 Chapter 5: MicroBlaze Instruction Set Architecture Logical Exclusive OR rD, rA, rB 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are XORed with the contents of register rB; the result is placed into register rD.
Page 284 Chapter 5: MicroBlaze Instruction Set Architecture xori Logical Exclusive OR with Immediate xori rD, rA, IMM 1 0 1 0 1 0 Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register rA are XOR’ed with the extended IMM field;...
Page 285: Appendix A: Performance And Resource Utilization
“IP Characterization and fMAX Margin System Methodology”, in the Vivado Design Suite User Guide: Designing With IP (UG986). Maximum Frequencies The maximum frequencies for the MicroBlaze core are provided in Table A-1. Zynq®-7000 results are expected to be similar to 7 series results.
Page 286: Resource Utilization
Appendix A: Performance and Resource Utilization Resource Utilization The MicroBlaze core resource utilization for various parameter configurations are measured for the following devices: • Virtex-7 (Table A-2) • Kintex-7 (Table A-3) • Artix-7 (Table A-4) • Virtex UltraScale (Table A-5) •...
Page 287 (MHz) Minimum Area Maximum Performance 3706 2916 Maximum Frequency Linux with MMU 3320 3069 Low-end Linux with MMU 2789 2445 Typical 1895 1630 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 288 (MHz) Minimum Area Maximum Performance 3706 2919 Maximum Frequency Linux with MMU 3320 3133 Low-end Linux with MMU 2789 2451 Typical 1895 1638 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 289 16384 8192 8192 C_DCACHE_BYTE_SIZE 4096 32768 4096 16384 8192 8192 C_DCACHE_LINE_LEN C_DCACHE_USE_WRITEBACK C_DEBUG_ENABLED C_DIV_ZERO_EXCEPTION C_M_AXI_D_BUS_EXCEPTION C_FPU_EXCEPTION C_FSL_EXCEPTION C_FSL_LINKS C_ICACHE_LINE_LEN C_ILL_OPCODE_EXCEPTION C_M_AXI_I_BUS_EXCEPTION C_MMU_DTLB_SIZE C_MMU_ITLB_SIZE MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 290 C_UNALIGNED_EXCEPTIONS C_USE_BARREL C_USE_DCACHE C_USE_DIV C_USE_EXTENDED_FSL_INSTR C_USE_FPU C_USE_HW_MUL C_USE_ICACHE C_USE_MMU C_USE_MSR_INSTR C_USE_PCMP_INSTR C_USE_REORDER_INSTR C_USE_BRANCH_TARGET_CACHE C_BRANCH_TARGET_CACHE_SIZE C_ICACHE_STREAMS C_ICACHE_VICTIMS C_DCACHE_VICTIMS C_ICACHE_FORCE_TAG_LUTRAM C_DCACHE_FORCE_TAG_LUTRAM C_ICACHE_ALWAYS_USED C_DCACHE_ALWAYS_USED C_D_AXI C_USE_INTERRUPT MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 291: Appendix B: Additional Resources And Legal Notices
7. AMBA 4 AXI4-Stream Protocol Specification, Version 1.0 (ARM IHI 0051A) 8. AMBA AXI and ACE Protocol Specification (ARM IHI 0022E) 9. MicroBlaze Debug Module (MDM) Product Guide (PG115) MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG984 (v2016.2) June 8, 2016 UG984 (v2016.1) April 6, 2016...
Page 292: Training Resources
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Page 293 Appendix B: Additional Resources and Legal Notices terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos.

Xilinx MicroBlaze Reference Manual

Chapter 1: Introduction

Chapter 2: Microblaze Architecture

Chapter 3: Microblaze Signal Interface Description

Chapter 4 : Microblaze Application Binary Interface

Chapter 5: Microblaze Instruction Set Architecture

Appendix A: Performance and Resource Utilization

Appendix B: Additional Resources and Legal Notices

Quick Links

Related Manuals for Xilinx MicroBlaze

Summary of Contents for Xilinx MicroBlaze

Table of Contents