Xilinx MicroBlaze Reference Manual page 102

Table 2-45: Performance Counter Status Register (PCSR)
Bits Name
1 Overflow
0 Full
Performance Counter Data Read Register
The Performance Counter Data Read Register (PCDRR) reads the sampled values of the
counters. To read the values of all configured counters, the register should be read
repeatedly. This register is a read-only register. Issuing a write request to the register does
nothing.
See the following figure and table.
X-Ref Target - Figure 2-29
31
Table 2-46: Performance Counter Data Read Register (PCDRR)
Bits Name
31:0 Item
Because a counter can have more than 32 bits, depending on the configuration, the register
might need to be read repeatedly to retrieve all information for a particular counter. This is
detailed in Table
Table 2-47: Performance Counter Data Items
Counter Type
Event Counter
Latency Counter
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
This bit is set when the counter has counted past its maximum value
This bit is set when a new latency counter event is started before the
previous event has finished. This indicates that the accuracy of the
measured values is reduced.
Figure 2-29: Performance Counter Data Read Register
Sampled counter value item
2-47.
Item
C_DEBUG_COUNTER_WIDTH
The number of times the event occurred
1
1 The number of times the event occurred
2 The sum of each event latency
The sum of each event latency squared
3
4 31:16 Minimum measured latency, 16 bits
15:0 Maximum measured latency, 16 bits
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Chapter 2: MicroBlaze Architecture
Description
Item
Description
Description
= 32
Reset Value
0
0
0
X19765-091117
Reset Value
0
102
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