Debug Interface Description; Trace Interface Description - Xilinx MicroBlaze Reference Manual

Debug Interface Description

The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor Debug
Module (MDM) IP core. The MDM is controlled by the Xilinx Microprocessor Debugger (XMD)
through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the
same time. The debug signals are grouped in the DEBUG bus. The debug signals on MicroBlaze are
listed in
Table 3-15: MicroBlaze Debug Signals
Dbg_Clk
Dbg_TDI
Dbg_TDO
Dbg_Reg_En
Dbg_Shift
Dbg_Capture
Dbg_Update
Debug_Rst
1. Updated for MicroBlaze v7.00: Dbg_Shift added and Debug_Rst included in DEBUG bus

Trace Interface Description

The MicroBlaze core exports a number of internal signals for trace purposes. This signal interface is
not standardized and new revisions of the processor may not be backward compatible for signal
selection or functionality. It is recommended that you not design custom logic for these signals, but
rather to use them via Xilinx provided analysis IP. The trace signals are grouped in the TRACE bus.
The current set of trace signals were last updated for MicroBlaze v7.30 and are listed in
The Trace exception types are listed in
Signal Name
Trace_Valid_Instr
1
Trace_Instruction
1
Trace_PC
1
Trace_Reg_Write
1
Trace_Reg_Addr
1
Trace_MSR_Reg
1,2
Trace_PID_Reg
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Table 3-15.
Signal Name
JTAG clock from MDM
JTAG TDI from MDM
JTAG TDO to MDM
Debug register enable from
MDM
JTAG BSCAN shift signal from
1
MDM
JTAG BSCAN capture signal
from MDM
JTAG BSCAN update signal
from MDM
Reset signal from MDM, active
1
high. Should be held for at least
1 Clk clock cycle.
Table 3-16: MicroBlaze Trace Signals
Description
Valid instruction on trace port.
Instruction code
Program counter
Instruction writes to the register file
Destination register address
Machine status register
Process identifier register
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Debug Interface Description
Description
std_logic
std_logic
std_logic
std_logic
std_logic
std_logic
std_logic
std_logic
Table 3-17. All unused Trace exception types are reserved.
VHDL Type
std_logic
std_logic_vector (0 to 31)
std_logic_vector (0 to 31)
std_logic
std_logic_vector (0 to 4)
std_logic_vector (0 to 14)
std_logic_vector (0 to 7)
VHDL Type Direction
input
input
output
input
input
input
input
input
Table 3-16.
Direction
output
output
output
output
output
2
output
output
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