Xilinx MicroBlaze Reference Manual page 82

When selecting cache sizes below 2 kB, distributed RAM is used to implement the Tag RAM
and Instruction RAM. Distributed RAM is always used to implement the Tag RAM, when
setting the parameter
with cache size 8 kB and less for 4 word cache-lines, with 16 kB and less for 8 word cache-
lines, and with 32 kB and less for 16 word cache-lines.
For example: in a MicroBlaze configured with
C_ICACHE_HIGHADDR=0x0030ffff
and
C_ICACHE_FORCE_TAG_LUTRAM=0
address, and the 4 kB cache uses 12 bits of byte address, thus the required address tag
width is: 16-12=4 bits. The total number of block RAM primitives required in this
configuration is: 2 RAMB16 for storing the 1024 instruction words, and 1 RAMB16 for 128
cache line entries, each consisting of: 4 bits of tag, 8 word-valid bits, 1 line-valid bit. In total
3 RAMB16 primitives.
The following figure shows the organization of Instruction Cache.
X-Ref Target - Figure 2-22
0
Instruction Cache Operation
For every instruction fetched, the instruction cache detects if the instruction address
belongs to the cacheable segment. If the address is non-cacheable, the cache controller
ignores the instruction and lets the
is cacheable, a lookup is performed on the tag memory to check if the requested address is
currently cached. The lookup is successful if: the word and line valid bits are set, and the tag
address matches the instruction address tag segment. On a cache miss, the cache controller
requests the new instruction over the instruction AXI4 interface (
the memory controller to return the associated cache line.
C_ICACHE_DATA_WIDTH
(128, 256 or 512 bits), or 512 bits.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
C_ICACHE_FORCE_TAG_LUTRAM
,
C_CACHE_BYTE_SIZE=4096
; the cacheable memory of 64 kB uses 16 bits of byte
Instruction Address Bits
Tag Address
Line Addr
Tag
RAM
Word Addr
Instruction
RAM
Figure 2-22: Instruction Cache Organization
M_AXI_IP
determines the bus data width, either 32 bits, an entire cache line
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Chapter 2: MicroBlaze Architecture
to 1. This parameter is only available
C_ICACHE_BASEADDR= 0x00300000
,
C_ICACHE_LINE_LEN=8
Cache Address
Tag
=
Valid (word and line)
Cache_instruction_data
or LMB complete the request. If the address
,
30 31
- -
Cache_Hit
X19759-091317
), and waits for
M_AXI_IC
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,
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