Xilinx MicroBlaze Reference Manual page 169

Table 3-15: MicroBlaze Debug Signals (Cont'd)
Signal Name
Dbg_Trace_Data
Dbg_Trace_Valid
Dbg_Trace_Ready
Dbg_Trace_Clk
4
Dbg_ARADDR
4
Dbg_ARREADY
4
Dbg_ARVALID
4
Dbg_AWADDR
4
Dbg_AWREADY
4
Dbg_AWVALID
4
Dbg_BREADY
4
Dbg_BRESP
4
Dbg_BVALID
4
Dbg_RDATA
4
Dbg_RREADY
4
Dbg_RRESP
4
Dbg_RVALID
4
Dbg_WDATA
4
Dbg_WREADY
4
Dbg_WVALID
4
DEBUG_ACLK
DEBUG_ARESET
1. Updated for MicroBlaze v7.00: Dbg_Shift added and Debug_Rst included in DEBUG bus
2. Updated for MicroBlaze v9.3: Dbg_Trig signals added to DEBUG bus
3. Updated for MicroBlaze v9.4: External Program Trace signal added to DEBUG bus
4. Updated for MicroBlaze v10.0: Parallel debug signals added to DEBUG bus
The parallel debug clock DEBUG_ACLK can usually be connected to the same source as Clk.
However, in case Clk is stopped to save power, the parallel debug clock should be
connected before the clock control buffer (to the Clock input signal in
Figure 3-3), otherwise debugging is not possible when Clk is stopped.
In most cases, the parallel debug reset DEBUG_ARESET can be directly connected to the
same source as Reset. However, in case software reset is implemented to only reset the
processor, parallel debug reset should not be affected by the software reset, to ensure that
debugging is not disturbed.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Description
External Program Trace data output to MDM std_logic_vector
3
External Program Trace valid to MDM
3
External Program Trace ready from MDM
3
External Program Trace clock from MDM
3
Read address from MDM
Read address ready to MDM
Read address valid from MDM
Write address from MDM
Write address ready to MDM
Write address valid from MDM
Write response ready to MDM
Write response to MDM
Write response valid from MDM
Read data to MDM
Read data ready to MDM
Read data response to MDM
Read data valid from MDM
Write data from MDM
Write data ready to MDM
Write data valid from MDM
Debug clock, must be synchronous to Clk
Debug reset, must be synchronous to Clk
4
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Chapter 3: MicroBlaze Signal Interface Description
VHDL Type
std_logic
std_logic
std_logic
std_logic_vector
std_logic
std_logic
std_logic_vector
std_logic
std_logic
std_logic
std_logic_vector
std_logic
std_logic_vector
std_logic
std_logic_vector
std_logic
std_logic_vector
std_logic
std_logic
std_logic
std_logic
Kind
output
output
input
input
parallel in
parallel out
parallel in
parallel in
parallel out
parallel in
parallel out
parallel out
parallel in
parallel out
parallel out
parallel out
parallel in
parallel in
parallel out
parallel in
parallel in
parallel in
Figure 3-2 and
170
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