Xilinx MicroBlaze Reference Manual page 69

Zone Protection
Zone protection is used to override the access protection specified in a TLB entry. Zones are
an arbitrary grouping of virtual pages with common access protection. Zones can contain
any number of pages specifying any combination of page sizes. There is no requirement for
a zone to contain adjacent pages.
The zone-protection register (ZPR) is a 32-bit register used to specify the type of protection
override applied to each of 16 possible zones. The protection override for a zone is encoded
in the ZPR as a 2-bit field.
The 4-bit zone-select field in a TLB entry (TLBLO[ZSEL]) selects one of the 16 zone fields
from the ZPR (Z0–Z15). For example, zone Z5 is selected when ZSEL = 0101.
Changing a zone field in the ZPR applies a protection override across all pages in that zone.
Without the ZPR, protection changes require individual alterations to each page translation
entry within the zone.
Unimplemented zones (when
UTLB Management
The UTLB serves as the interface between the processor MMU and memory-management
software. System software manages the UTLB to tell the MMU how to translate virtual
addresses into physical addresses. When a problem occurs due to a missing translation or
an access violation, the MMU communicates the problem to system software using the
exception mechanism. System software is responsible for providing interrupt handlers to
correct these problems so that the MMU can proceed with memory translation.
Software reads and writes UTLB entries using the MFS and MTS instructions, respectively.
With PAE enabled, the MFSE and MTSE instructions are used to access the most significant
part of the real page number. These instructions use the TLBX register index (numbered 0 to
63) corresponding to one of the 64 entries in the UTLB. The tag and data portions are read
and written separately, so software must execute two MFS or MTS instructions, and also an
additional MFSE or MTSE instruction when PAE is enabled, to completely access an entry.
The UTLB is searched for a specific translation using the TLBSX register. TLBSX locates a
translation using an effective address and loads the corresponding UTLB index into the
TLBX register.
Individual UTLB entries are invalidated using the MTS instruction to clear the valid bit in the
tag portion of a TLB entry (TLBHI[V]).
When
C_FAULT_TOLERANT
a parity error, a TLB miss exception occurs. To avoid accumulating errors in this case, each
entry in the UTLB should be periodically invalidated.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
< 16) are treated as if they contained 11.
C_MMU_ZONES
is set to 1, the UTLB block RAM is protected by parity. In case of
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