Xilinx MicroBlaze Reference Manual page 294

swi Store Word Immediate
rD, rA, IMM
swi
1 1 1 1 1 0
0
6
Description
Stores the contents of register rD, into the word aligned memory location that results from adding the
contents of registers rA and the value IMM, sign-extended to 32 bits.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
An unaligned data access exception occurs if the two least significant bits in the address are not zero.
Pseudocode
←
Addr (rA) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC] 10010;ESR[S]
←
MSR[UMS]
else if Access_Protected(Addr) and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if Addr[30:31]
←
ESR[EC]
else
←
Mem(Addr)
Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
• 1 cycle with
• 2 cycles with
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
←
1
←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 1; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
←
00001; ESR[W] 1; ESR[S]
(rD)[0:31]
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
"imm"
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Chapter 5: MicroBlaze Instruction Set Architecture
16
←
MSR[VM]; MSR[UM]
←
No-access-allowed
←
MSR[VM]; MSR[UM] 0; MSR[VM]
← ←
1; ESR[Rx]
for details on using 32-bit immediate values.
IMM
←
0; MSR[VM] 0
←
0
rD
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