Xilinx MicroBlaze Reference Manual page 137

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_DP_RVALID
M_AXI_DP_RREADY
M_AXI_IP_AWID
M_AXI_IP_AWADDR
M_AXI_IP_AWLEN
M_AXI_IP_AWSIZE
M_AXI_IP_AWBURST
M_AXI_IP_AWLOCK
M_AXI_IP_AWCACHE
M_AXI_IP_AWPROT
M_AXI_IP_AWQOS
M_AXI_IP_AWVALID
M_AXI_IP_AWREADY
M_AXI_IP_WDATA
M_AXI_IP_WSTRB
M_AXI_IP_WLAST
M_AXI_IP_WVALID
M_AXI_IP_WREADY
M_AXI_IP_BID
M_AXI_IP_BRESP
M_AXI_IP_BVALID
M_AXI_IP_BREADY
M_AXI_IP_ARID
M_AXI_IP_ARADDR
M_AXI_IP_ARLEN
M_AXI_IP_ARSIZE
M_AXI_IP_ARBURST
M_AXI_IP_ARLOCK
M_AXI_IP_ARCACHE
M_AXI_IP_ARPROT
M_AXI_IP_ARQOS
M_AXI_IP_ARVALID
M_AXI_IP_ARREADY
M_AXI_IP_RID
M_AXI_IP_RDATA
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Interface I/O
I Slave Read valid
M_AXI_DP
Master Read ready
O
M_AXI_DP
O Master Write address ID
M_AXI_IP
O Master Write address
M_AXI_IP
Master Burst length
O
M_AXI_IP
O Master Burst size
M_AXI_IP
O Master Burst type
M_AXI_IP
O Master Lock type
M_AXI_IP
Master Cache type
O
M_AXI_IP
O Master Protection type
M_AXI_IP
O Master Quality of Service
M_AXI_IP
Master Write address valid
O
M_AXI_IP
I Slave Write address ready
M_AXI_IP
O Master Write data
M_AXI_IP
O Master Write strobes
M_AXI_IP
Master Write last
O
M_AXI_IP
O Master Write valid
M_AXI_IP
I Slave Write ready
M_AXI_IP
I Slave Response ID
M_AXI_IP
Slave Write response
I
M_AXI_IP
I Slave Write response valid
M_AXI_IP
O Master Response ready
M_AXI_IP
Master Read address ID
O
M_AXI_IP
O Master Read address
M_AXI_IP
O Master Burst length
M_AXI_IP
O Master Burst size
M_AXI_IP
Master Burst type
O
M_AXI_IP
O Master Lock type
M_AXI_IP
O Master Cache type
M_AXI_IP
Master Protection type
O
M_AXI_IP
O Master Quality of Service
M_AXI_IP
O Master Read address valid
M_AXI_IP
I Slave Read address ready
M_AXI_IP
Slave Read ID tag
I
M_AXI_IP
I Slave Read data
M_AXI_IP
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Chapter 3: MicroBlaze Signal Interface Description
Description
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