Xilinx MicroBlaze Reference Manual page 48

Table 2-35: Processor Version Register 11 (PVR11)
Bits Name
0:1 MMU
2:4 ITLB
5:7 DTLB
8:9 TLBACC
10:14 ZONES
15 PRIVINS
16:16 Reserved
17:31 RSTMSR
Table 2-36: Processor Version Register 12 (PVR12)
Bits Name
0:31 VECTORS
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Description
Use MMU:
0 = None
1 = User Mode
Instruction Shadow TLB size
Data Shadow TLB size
TLB register access:
0 = Minimal
1 = Read
Number of memory protection zones
Privileged instructions:
0 = Full protection
1 = Allow stream instructions
Reserved for future use
Reset value for MSR
Description
Location of MicroBlaze vectors
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Chapter 2: MicroBlaze Architecture
2 = Protection
3 = Virtual
2 = Write
3 = Full
Value
C_USE_MMU
log2(C_MMU_ITLB_SIZE)
log2(C_MMU_DTLB_SIZE)
C_MMU_TLB_ACCESS
C_MMU_ZONES
C_MMU_PRIVILEGED_INSTR
0
C_RESET_MSR_IE << 2 |
C_RESET_MSR_BIP << 4 |
C_RESET_MSR_ICE << 6 |
C_RESET_MSR_DCE << 8 |
C_RESET_MSR_EE << 9 |
C_RESET_MSR_EIP << 10
Value
C_BASE_VECTORS
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