Xilinx MicroBlaze Reference Manual page 258

Latency
• 1 cycle
Notes
When writing MSR using MTS, all bits take effect one cycle after the instruction has been executed. An
MTS instruction writing MSR should never be followed back-to-back by an instruction that uses the
MSR content. When clearing the IE bit, it is guaranteed that the processor will not react to any
interrupt for the subsequent instructions. When setting the EIP or BIP bit, it is guaranteed that the
processor will not react to any interrupt or normal hardware break for the subsequent instructions.
To refer to special purpose registers in assembly language, use rmsr for MSR, rfsr for FSR, rslr for SLR,
rshr for SHR, rpid for PID, rzpr for ZPR, rtlblo for TLBLO, rtlbhi for TLBHI, rtlbx for TLBX, and rtlbsx for
TLBSX.
The PC, ESR, EAR, BTR, EDR and PVR0 - PVR12 cannot be written by the MTS instruction.
The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0.
The SLR and SHR are only valid as a destination if the MicroBlaze parameter
C_USE_STACK_PROTECTION is set to 1.
PID, ZPR and TLBSX are only valid as destinations when the parameter C_USE_MMU > 1 (User Mode)
and the parameter C_MMU_TLB_ACCESS > 1 (Read). TLBLO, TLBHI and TLBX are only valid as
destinations when the parameter C_USE_MMU > 1 (User Mode).
When changing MSR[VM] or PID the instruction must always be followed by a synchronizing branch
instruction, for example BRI 4.
After writing to TLBHI in order to invalidate one or more UTLB entries, an MBAR 1 instruction must be
issued to ensure that coherency is preserved in a coherent multi-processor system.
When PAE is enabled, the entire TLBLO register must be written, by first using the extended
instruction to write the most significant bits immediately followed by the least significant bits.
The extended instruction is only valid if MicroBlaze is configured to use the MMU in virtual mode
(C_USE_MMU = 3) and extended address (C_ADDR_SIZE > 32).
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 5: MicroBlaze Instruction Set Architecture
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