Xilinx MicroBlaze Reference Manual page 36

PID is also used when accessing a TLB entry:
• When writing Translation Look-Aside Buffer High (TLBHI) the value of PID is stored in
the TID field of the TLB entry
• When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID
The following figure illustrates the PID register and
reset values.
X-Ref Target - Figure 2-12
0
Table 2-18: Process Identifier Register (PID)
Bits Name
0:23 Reserved
24:31 PID
Zone Protection Register (ZPR)
The Zone Protection Register is used to override MMU memory protection defined in TLB
entries. It is controlled by the
is only implemented if
to 0 (Performance) or 2 (Frequency), and if the number of specified memory protection
zones is greater than zero (
number of specified memory protection zones (
MFS and MTS instructions, the ZPR is specified by setting Sa = 0x1001. The register is
accessible according to the memory management special registers parameter
C_MMU_TLB_ACCESS
The following figure illustrates the ZPR register and
and reset values.
X-Ref Target - Figure 2-13
0 2 4
ZP0 ZP1 ZP2
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
RESERVED
Figure 2-12: PID
Used to uniquely identify a software process during MMU
address translation.
Read/Write
C_USE_MMU
is greater than 1 (User Mode),
C_USE_MMU
C_MMU_ZONES
.
6 8 10 12 14
ZP3 ZP4 ZP5 ZP6
Figure 2-13: ZPR
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Chapter 2: MicroBlaze Architecture
Table 2-18
Description
configuration option on MicroBlaze. The register
> ). The implemented register bits depend on the
0
C_MMU_ZONES
Table 2-19
16 18 20 22
ZP7 ZP8 ZP9 ZP10 ZP11
provides bit descriptions and
24
PID
X19749-091317
Reset Value
0x00
C_AREA_OPTIMIZED
). When accessed with the
provides bit descriptions
24 26 28 30
ZP12 ZP13 ZP14 ZP15
X19750-091317
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31
is set
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