Xilinx MicroBlaze Reference Manual page 229

fdiv Floating-Point Arithmetic Division
fdiv rD, rA, rB
0 1 0 1 1 0
0
6
Description
The floating-point value in rB is divided by the floating-point value in rA and the result is placed into
register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
←
(rD) 0xFFC00000
←
FSR[DO]
←
ESR[EC]
else
if isSigNaN(rA) or isSigNaN(rB) or (isZero(rA) and isZero(rB)) or
(isInfinite(rA) and isInfinite(rB)) then
←
(rD) 0xFFC00000
← 1
FSR[IO]
←
ESR[EC]
else if isQuietNaN(rA) or isQuietNaN(rB) then
←
(rD) 0xFFC00000
else if isZero(rA) and not isInfinite(rB) then
←
(rD) signInfinite((rB)/(rA))
←
FSR[DZ]
←
ESR[EC]
else if isDnz((rB) / (rA)) then
←
(rD) signZero((rB) / (rA))
←
FSR[UF]
←
ESR[EC]
else if isNaN((rB)/(rA)) then
←
(rD) signInfinite((rB) / (rA))
←
FSR[OF]
←
ESR[EC]
else
←
(rD) (rB) / (rA)
Registers Altered
• rD, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
• FSR[IO,UF,OF,DO,DZ]
Latency
• 28 cycles with
• 30 cycles with
• 24 cycles with
Note
This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Divide
rD rA
11
1
00110
00110
1
00110
1
00110
1
00110
=0
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
=2
C_AREA_OPTIMIZED
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 1 1 0 0 0 0 0 0 0
16 21 31
230
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