Xilinx MicroBlaze Reference Manual page 78

The BIP bit in the MSR is automatically cleared when executing the
The signal must be kept asserted until the break has occurred, and deasserted
Ext_BRK
before the RTBD instruction is executed. The
clock cycle.
Software Breaks
To perform a software break, use the
MicroBlaze Instruction Set Architecture
As a special case, when
executed, a software breakpoint is signaled to the debugger; for example, the Xilinx System
Debugger (XSDB) tool, irrespective of the value of
in the MSR is not set.
Latency
The time it takes the MicroBlaze processor to enter a break service routine from the time
the break occurs depends on the instruction currently in the execution stage and the
latency to the memory storing the break vector.
Equivalent Pseudocode
←
r16 PC
←
PC C_BASE_VECTORS + 0x00000018
←
MSR[BIP]
←
MSR[UMS]
Reservation
Interrupt
MicroBlaze supports one external interrupt source (connected to the
The processor only reacts to interrupts if the Interrupt Enable (IE) bit in the Machine Status
Register (MSR) is set to 1. On an interrupt, the instruction in the execution stage completes
while the instruction in the decode stage is replaced by a branch to the interrupt vector.
This is either address
address supplied by the Interrupt Controller.
The interrupt return address (the PC associated with the instruction in the decode stage at
the time of the interrupt) is automatically loaded into general purpose register R14. In
addition, the processor also disables future interrupts by clearing the IE bit in the MSR. The
IE bit is automatically set again when executing the RTID instruction.
Interrupts are ignored by the processor if either of the break in progress (
in progress (
EIP
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
brk
C_DEBUG_ENABLED
1
←
MSR[UM], MSR[UM] 0, MSR[VMS]
←
0
C_BASE_VECTORS
) bits in the MSR are set to 1.
www.xilinx.com
Chapter 2: MicroBlaze Architecture
signal must only be asserted one
Ext_NM_BRK
and instructions. Refer to
brki
for detailed information on software breaks.
is greater than zero, and "
C_BASE_VECTORS
←
MSR[VM], MSR[VM]
+ 0x10, or with low-latency interrupt mode, the
instruction.
RTBD
Chapter 5,
is
brki rD,0x18"
. In this case the BIP bit
←
0
input port).
Interrupt
) or exception
BIP
78
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